Integrated fan-out structure with guiding trenches in buffer layer

Patent metadata

Field	Value
Publication number	US-9425121-B2
Application number	US-201314024311-A
Country	US
Kind code	B2
Filing date	Sep 11, 2013
Priority date	Sep 11, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.

First claim

What is claimed is:

1. A package comprising:
a bottom package comprising:
a molding compound;
a buffer layer over and contacting the molding compound;
a through-via penetrating through the molding compound;
a device die molded in the molding compound; and
a guiding trench extending from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die;

a top package over and bonded to the bottom package, wherein the top package and the bottom package have a gap therebetween; and
an underfill filling outer portions of the gap, wherein the underfill extends into the guiding trench, and wherein a center portion of the gap is free from the underfill.

2. The package of claim 1 , wherein the underfill encircles the center portion of the gap.

3. The package of claim 1 , wherein the center portion of the gap overlaps an entirety of the device die.

4. The package of claim 1 , wherein the underfill is in physical contact with the molding compound.

5. The package of claim 1 , wherein the guiding trench forms a ring, and wherein the guiding trench encircles a center portion of the buffer layer, with the center portion of the buffer layer overlapping an entirety of the device die.

6. The package of claim 1 further comprising an adhesive layer between the device die and the buffer layer, and wherein the adhesive layer is in contact with a back surface of a semiconductor substrate of the device die and the buffer layer.

7. The package of claim 1 , wherein the center portion of the gap free from the underfill has a lateral dimension greater than a respective lateral dimension of the device die.

8. A package comprising:
a bottom package comprising:
a molding compound comprising a planar top surface and a planar bottom surface;
a device die molded in the molding compound;
a planar dielectric layer over and contacting the planar top surface of the molding compound;
a through-via penetrating through the molding compound; and
a first guiding trench in the planar dielectric layer;

a top package bonded to the bottom package, wherein the top package is spaced apart from the bottom package by a gap, and wherein the first guiding trench is connected to the gap; and
an underfill filling a perimeter of the gap and at least a portion of the first guiding trench, and wherein a center portion of the gap is encircled by the underfill, and wherein the center portion of the gap forms an empty space.

9. The package of claim 8 , wherein the first guiding trench forms a ring encircling a center portion of the planar dielectric layer, and wherein the center portion of the planar dielectric layer overlaps an entirety of the device die.

10. The package of claim 8 , wherein the bottom package further comprises:
redistribution lines underlying the molding compound, wherein the redistribution lines are electrically coupled to the through-via and the device die.

11. The package of claim 8 further comprising a second guiding trench in the planar dielectric layer, wherein the second guiding trench encircles the first guiding trench.

12. The package of claim 8 , wherein the underfill penetrates through the planar dielectric layer to contact the molding compound.

13. The package of claim 8 , wherein the guiding trench extends partially into the planar dielectric layer, with a lower part of the planar dielectric layer remaining underlying the guiding trench.

14. The package of claim 8 , wherein the planar dielectric layer comprises a polymer.

15. A package comprising:
a bottom package comprising:
an encapsulating material;
a device die encapsulated in the encapsulating material;
at least one dielectric layer over and contacting a top surface of the encapsulating material; and
a first guiding trench in the at least one dielectric layer, wherein the first guiding trench encircles a region directly over the device die;

a top package over and bonded to the bottom package; and
an underfill between the bottom package and the top package, wherein the underfill fills the first guiding trench, and the region directly over the device die forms and air gap encircled by the underfill.

16. The package of claim 15 , wherein an inner edge of the underfill facing the air gap is substantially aligned to an inner edge of the air gap.

17. The package of claim 15 , wherein the first guiding trench forms a full ring, and the first guiding trench extends to the encapsulating material.

18. The package of claim 15 , wherein the first guiding trench does not overlap any region that is directly over the device die.

19. The package of claim 15 further comprising a second guiding trench in the at least one dielectric layer, wherein the second guiding trench encircles the first guiding trench.

20. The package of claim 15 further comprising a through-via penetrating through the encapsulating material, wherein a top surface of the through-via is in contact with a bottom surface of the at least one dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Po-Hao
• Hsu Feng-Cheng
• Cheng Li-Hui
• Hung Jui-Pin
• Lin Jing-Cheng

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60 Primary

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title