Semiconductor device and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9425065-B2
Application number	US-201514687619-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Sep 29, 2011
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
placing an insulating substrate in at least one mold having at least one wiring pattern-forming cavity for forming a wiring pattern directly on said insulating substrate, and also having a junction terminal-forming cavity for forming a junction terminal directly on said insulating substrate and extending upward from said insulating substrate;
pouring aluminum into the at least one wiring pattern-forming cavity and into the junction terminal-forming cavity, the poured aluminum being at least partially molten aluminum; and
cooling the poured aluminum, thereby forming at a same time both the wiring pattern and the junction terminal directly on said insulating substrate, the junction terminal having an uninterrupted microstructure from one end formed directly on said insulating substrate to another end extending upward from said insulating substrate.

2. The method according to claim 1 ,
wherein the at least one mold has a power terminal-forming cavity for forming a power terminal directly on said insulating substrate and extending upward from said insulating substrate,
wherein the pouring includes pouring the aluminum into said power terminal-forming cavity, and
wherein the cooling the poured aluminum includes forming the power terminal at the same time as both the wiring pattern and the junction terminal directly on said insulating substrate.

3. The method according to claim 2 , wherein the power terminal has an uninterrupted microstructure from one end formed directly on said insulating substrate to another end extending upward from said insulating substrate.

4. The method according to claim 3 ,
wherein the at least one mold has a bottom surface pattern-forming cavity for forming a bottom surface pattern directly on said insulating substrate on a side thereof opposite to the wiring pattern-forming cavity,
wherein the pouring includes pouring the aluminum into said bottom surface pattern-forming cavity, and
wherein the cooling the poured aluminum includes forming the bottom surface pattern at the same time as the wiring pattern, the junction terminal, and the power terminal, directly on said insulating substrate.

5. The method according to claim 4 , further comprising providing a molded resin covering the insulating substrate, the wiring pattern, the junction terminal, and the power terminal, the molded resin outwardly exposing said another end of the junction terminal, said another end of the power terminal, and a surface of the bottom surface pattern that is opposite that which is formed directly on said insulating substrate.

6. The method according to claim 4 , further comprising forming an adhesive primer on a surface of the wiring pattern, a surface of the insulating substrate, and at least one of a surface of the junction terminal, a surface of the power terminal, and a surface of the bottom surface pattern.

7. The method according to claim 5 , wherein a coefficient of linear expansion of the molded resin is equal to a coefficient of linear expansion of the wiring pattern.

8. The method according to claim 1 , further comprising securing a semiconductor chip to the formed wiring pattern.

9. The method according to claim 1 , wherein an aspect ratio of the junction terminal from the one end to the another end is greater than or equal to 2.

10. The method according to claim 2 , wherein an aspect ratio of the power terminal from the one end to the another end is greater than or equal to 2.

11. The method according to claim 3 , further comprising, after the forming the power terminal, bending the power terminal at a region thereof closer to the another end than to the one end.

Assignees

• Mitsubishi Electric Corp

Inventors

• Otsuki Takami
• Obara Taichi
• Goto Akira

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title