Circuits, methods, and media for detecting and countering aging degradation in memory cells

Patent metadata

Field	Value
Publication number	US-9424952-B1
Application number	US-201615018834-A
Country	US
Kind code	B1
Filing date	Feb 8, 2016
Priority date	Feb 7, 2015
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

First claim

What is claimed is:

1. A circuit for measuring threshold voltages of transistors in a memory device bitcell, comprising:
a multiplexer that has a plurality of pairs of inputs, each connected to a different pair of bitlines of the memory device, and that has an output connected to a pair of bitline terminals;
a first plurality of interconnected switches that are connected to a ground, a test voltage, a sense voltage node (V SEN ), the pair of bitline terminals, and a pair of sensor terminals;
a second plurality of interconnected switches that are connected to the test voltage, the ground, the sense voltage node (V SEN ), a positive voltage connection, an n-well connection, and a ground power connection of the bitcell; and
a zero-V TH thick-oxide NMOS transistor having a gate, a drain, and a source, wherein the gate is connected to the source, the source is connected to the gate and one of the pair of sensor terminals; and the drain is connected to another of the pair of sensor terminals,
wherein, when in a first configuration of the multiplexer, the first plurality of interconnected switches, and the second plurality of interconnected switches, a gate of a first transistor of the bitcell and one of a drain and a source of the first transistor of the bitcell are coupled to the test voltage, another of the drain and the source of the first transistor of the bitcell is coupled to the drain of the zero-V TH thick-oxide NMOS transistor, and the gate and the source of the zero-V TH thick-oxide NMOS transistor are coupled to ground.

2. The circuit of claim 1 , wherein when in a second configuration of the multiplexer, the first plurality of interconnected switches, and the second plurality of interconnected switches, a gate of a second transistor of the bitcell and one of a drain and a source of the second transistor of the bitcell are coupled to ground, another of the drain and the source of the second transistor of the bitcell is coupled to the gate and the source of the zero-V TH thick-oxide NMOS transistor, and the drain of the zero-V TH thick-oxide NMOS transistor is coupled to the test voltage.

3. The circuit of claim 2 , further comprising a hardware processor that uses a measurement of a voltage at the sense voltage node (V SEN ) to estimate a threshold voltage of the second transistor.

4. The circuit of claim 1 , further comprising a hardware processor that uses a measurement of a voltage at the sense voltage node (V SEN ) to estimate a threshold voltage of the first transistor.

5. The circuit of claim 1 , wherein the bitcell includes six different transistors, and each of six different configurations of the multiplexer, the first plurality of interconnected switches, and the second plurality of interconnected switches results in a coupling of the zero-V TH thick-oxide NMOS transistor to a different one of the six different transistors of the bitcell.

6. The circuit of claim 5 , further comprising a hardware processor that uses measurements of voltages at the sense voltage node (V SEN ) in each of the six different configurations to estimate data retention voltage (DRV) of the bitcell.

7. The circuit of claim 6 , wherein the hardware process estimates DRV polarity based on a vector X 1 =(V PL −V PR , V NL −V NR ), where V PL is the value of V SEN when a transistor PL in the bitcell is a device under test, V PR is the value of V SEN when a transistor PR in the bitcell is a device under test, V NL is the value of V SEN when a transistor NL in the bitcell is a device under test, and V NR is the value of V SEN when transistor NR is the device under test.

8. The circuit of claim 6 , wherein the hardware process estimates DRV magnitude based on a vector X 2 =(max(V PL , V PR ), max(V NL , V NR ), max(V AL , V AR )), where V PL is the value of V SEN when a transistor PL in the bitcell is a device under test, V PR is the value of V SEN when a transistor PR in the bitcell is a device under test, V NL is the value of V SEN when a transistor NL in the bitcell is a device under test, V NR is the value of V SEN when transistor NR is the device under test, V PL is the value of V SEN when a transistor PL is a device under test, and V PR is the value of V SEN when a transistor PR is a device under test.

9. The circuit of claim 5 , further comprising a hardware processor that uses measurements of voltages at the sense voltage node (V SEN ) in each of the six different configurations to estimate read access time (T ACC ) of the bitcell.

10. The circuit of claim 9 , wherein the hardware process estimates T ACC polarity based on a vector X 3 =(V PL −V PR , V NL −V NR , V AL −V AR , V OS ), where V PL is the value of V SEN when a transistor PL in the bitcell is a device under test; V PR is the value of V SEN when a transistor PR in the bitcell is a device under test; V NL is the value of V SEN when a transistor NL in the bitcell is a device under test; V NR is the value of V SEN when a transistor NR in the bitcell is a device under test; V AL is the value of V SEN when a transistor AL in the bitcell is a device under test; V AR is the value of V SEN when a transistor AR in the bitcell is a device under test; and a V OS is a sense amplifier's input-referred offset voltage.

11. The circuit of claim 9 , wherein the hardware process estimates T ACC magnitude based on a vector X 4 =(max(V PL , V PR ), max(V NL , V NR ), max(V AL , V AR ), max(V OS )), where V PL is the value of V SEN when a transistor PL in the bitcell is a device under test, V PR is the value of V SEN when a transistor PR in the bitcell is a device under test; V NL is the value of V SEN when a transistor NL in the bitcell is a device under test; and V NR is the value of V SEN when a transistor NR in the bitcell is a device under test, V AL is the value of V SEN when a transistor AL in the bitcell is a device under test, V AR is the value of V SEN when a transistor AR in the bitcell is a device under test, V OS is a sense amplifier's input-referred offset voltage.

Assignees

• Seok Mingoo
• Kinget Peter
• Yang Teng
• Univ Columbia

Inventors

• Seok Mingoo
• Kinget Peter
• Yang Teng

Classifications

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C29/50016

  of retention · CPC title

• G11C29/50004 Primary

  of threshold voltage · CPC title

• G11C29/50012

  of timing · CPC title