Nonvolatile memory device and method of erasing the same

Patent metadata

Field	Value
Publication number	US-9424940-B1
Application number	US-201614987178-A
Country	US
Kind code	B1
Filing date	Jan 4, 2016
Priority date	Jun 10, 2015
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A nonvolatile memory device includes a substrate, a plurality of memory cells stacked in a direction perpendicular to the substrate, word lines connected to the memory cells, a ground select transistor between the memory cells and the substrate, a ground select transistor between the memory cells and the substrate, a ground select line connected to the ground select transistor, a bit line on the memory cells, and a string select transistor between the memory cells and the bit line. In an erase operation, the ground select line is floated at a time when a specific time passes after the erase voltage is provided to the substrate. And the ground select line is floated at different times depending on a temperature.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array including at least one bit line and a plurality of cell strings on a substrate, each of the cell strings including a plurality of memory cells stacked on each other in a direction perpendicular to the substrate, a ground select transistor between the memory cells and the substrate, and a string select transistor on the memory cells between the memory cells and one of the at least one bit line;
an address decoder configured to provide an erase voltage to the substrate during an erase operation, the address decoder being configured to float a ground select line connected to the ground select transistor in at least one of the cell strings after a specific time passes after the address decoder provides the erase voltage to the substrate during the erase operation;
a voltage generator configured generate the erase voltage, the voltage generator being configured to change the erase voltage based on a temperature using first temperature information and ground select line transition information based on a feedback voltage corresponding to the erase voltage and second temperature information; and
a control logic configured to generate a ground select line control signal based on the ground select line transition information,
the address decoder being configured to float the ground select line according to the ground select line control signal.

2. The nonvolatile memory device of claim 1 , wherein the voltage generator is configured to generate the erase voltage so that the erase voltage increases or decreases by an offset voltage according to the first temperature information.

3. The nonvolatile memory device of claim 1 , wherein
the voltage generator is configured to generate a first level of the erase voltage at a first temperature and to generate a second level of the erase voltage at a second temperature, and
the second level of the erase voltage is higher than the first level of the erase voltage if the first temperature is higher than the second temperature.

4. The nonvolatile memory device of claim 3 , wherein
the control logic is configured to generate the ground select line control signal so that the address decoder floats the ground select line at a later time at the second temperature rather than at the first temperature.

5. The nonvolatile memory device of claim 1 , wherein the voltage generator is configured to generate the feedback voltage corresponding to the erase voltage according to a voltage division of a plurality of resistors.

6. The nonvolatile memory device of claim 1 , wherein the voltage generator includes:
a voltage generating circuit configured to generate the erase voltage and the feedback voltage; and
a ground select line transition determining circuit configured to generate the ground select line transition information.

7. The nonvolatile memory device of claim 6 , wherein
the voltage generating circuit includes a regulator configured to receive an erase target voltage,
the voltage generating circuit is configured to compensate the erase target voltage according to the first temperature information, and
the regulator is configured to generate a pump control signal based on comparing the compensated erase target voltage with the feedback voltage.

8. The nonvolatile memory device of claim 7 , wherein
the regulator is configured to generate the pump control signal at a first level if the feedback voltage is smaller than the compensated erase target voltage,
the regulator is configured to generate the pump control signal at a second level if the feedback voltage is equal to the compensated erase target voltage, and
the regulator is configured to generate the pump control signal at a third level if the feedback voltage is greater than the compensated erase target voltage,
wherein the first level is greater than the second level, and the second level is greater than the third level.

9. The nonvolatile memory device of claim 7 , wherein the voltage generating circuit includes a charge pump configured to generate the erase voltage according to the pump control signal.

10. The nonvolatile memory device of claim 6 , wherein
the ground select line transition determining circuit includes a regulator configured to receive a ground select line target voltage,
the regulator is configured to compensate the ground select line target voltage according to the second temperature information, and
the regulator is configured to generate the ground select line transition information based on comparing the compensated ground select line target voltage with the feedback voltage.

11. The nonvolatile memory device of claim 10 , wherein
the regulator is configured to generate the ground select line transition information at a first level if the feedback voltage is smaller than the compensated ground select line target voltage,
the regulator is configured to generate the ground select line transition information at a second level if the feedback voltage is equal to the compensated ground select line target voltage, and
the regulator is configured to generate the ground select line transition information at a third level if the feedback voltage is greater than the compensated ground select line target voltage,
wherein the first level is greater than the second level, and the second level is greater than the third level.

12. A nonvolatile memory device comprising:
word lines connected to a plurality of memory cells stacked in a direction perpendicular to a substrate;
a ground select line connected to a ground select transistor provided between the memory cells and the substrate; and
a string select line connected to a string select transistor provided between the memory cells and a bit line,
wherein in an erase operation, the ground select line is floated at a time when a specific time passes after the erase voltage is provided to the substrate, and
wherein the ground select line is floated at different times depending on a temperature.

13. The nonvolatile memory device of claim 12 , wherein the erase voltage is controlled to increase or decrease by an offset voltage according to a temperature based on first temperature information.

14. The nonvolatile memory device of claim 13 , wherein ground select line transition information is generated based on a feedback voltage corresponding to the erase voltage compensated by the first temperature information and second temperature information, and
wherein the ground select line is floated at different times according to a temperature based on the ground select line transition information.

15. The nonvolatile memory device of claim 12 , wherein a first temperature is higher than a second temperature and the erase voltage is generated to have a higher level at the second temperature rather than at the first temperature, and
wherein the ground select line is floated at a later time at the second temperature rather than at the first temperature.

16. A nonvolatile memory device comprising:
a memory cell array including a plurality of cell strings on a substrate, each of the cell strings including a plurality of memory cells serially connected to each other between a ground select transistor and a string select transistor;
a read and write circuit connected to the memory cell array through at least one bit line;
an address decoder connected to the memory cell array through a string selection line, word lines, and a ground selection line,
the address decoder being configured to provide an erase voltage to the substrate beginning at a first ti

Assignees

• Choo Gyosoo
• Kang Dongku
• Seo Sungwhan
• Kim Moosung
• Samsung Electronics Co Ltd

Inventors

• Choo Gyosoo
• Kang Dongku
• Seo Sungwhan
• Kim Moosung

Classifications

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title