Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit

Patent metadata

Field	Value
Publication number	US-9424045-B2
Application number	US-201313752621-A
Country	US
Kind code	B2
Filing date	Jan 29, 2013
Priority date	Jan 29, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

First claim

We claim:

1. A data processing apparatus, comprising:
execution circuitry comprising a number of execution units, including a first operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction, where N is an integer greater than 0;
decoder circuitry configured to decode each instruction to be executed by the execution circuitry in order to generate for each instruction at least one control data block identifying an operation to be performed by the execution circuitry in order to execute said instruction;
issue queue circuitry providing an issue queue having a plurality of slots, each slot configured to store one control data block generated by the decoder circuitry along with up to M bits of operand data associated with that control data block, where M is less than N and is an integer greater than 0;
the issue queue circuitry configured to issue control data blocks and associated operand data from the issue queue to the execution circuitry for processing;
the decoder circuitry being responsive to receiving an instruction suitable for execution by said first operand execution unit and requiring more than M bits, but no more than N bits, of operand data to be processed during execution, to generate at least two re-combineable control data blocks for said instruction suitable for execution by said first operand execution unit;
the issue queue circuitry configured to allocate a slot in the issue queue for each of said at least two re-combineable control data blocks and up to M bits of associated operand data, and to mark those allocated slots to identify that they contain re-combineable control data blocks;
the issue queue circuitry being configured, responsive to a determination that said at least two re-combineable control data blocks are to be issued to said first operand execution unit, to re-combine said at least two re-combineable control data blocks into a combined control data block, and to issue the combined control data block to said first operand execution unit along with the operand data contained in each of the allocated slots for said at least two re-combineable control data blocks.

2. A data processing apparatus as claimed in claim 1 , wherein said issue queue circuitry maintains status information for each slot of said issue queue, said status information identifying which slots have been allocated for said at least two re-combineable control data blocks.

3. A data processing apparatus as claimed in claim 2 , wherein said status information comprises a combine field associated with each slot, the issue queue circuitry being configured to set a value in each combine field to identify whether the associated slot contains one of said re-combineable control data blocks.

4. A data processing apparatus as claimed in claim 3 , wherein for at least one of the slots allocated for said at least two re-combineable data blocks, the issue queue circuitry is configured to identify within the associated combine field each other slot that contains one of said at least two re-combineable control data blocks.

5. A data processing apparatus as claimed in claim 2 , wherein said status information includes ready for execution information set by the issue queue circuitry to identify which slots contain a control data block that is ready to be executed by the execution circuitry.

6. A data processing apparatus as claimed in claim 5 , wherein for the slots allocated for said at least two re-combineable control data blocks, the issue queue circuitry is configured to defer setting the ready for execution information for any of those slots until all of said at least two re-combineable control data blocks are ready for execution.

7. A data processing apparatus as claimed in claim 6 , wherein when all of said at least two re-combineable control data blocks are ready for execution, the issue queue circuitry is configured to set the ready for execution information to identify, as ready for execution, a predetermined one of the slots allocated for said at least two re-combineable control data blocks.

8. A data processing apparatus as claimed in claim 5 , wherein said issue queue circuitry determines, for each slot, whether the control data block allocated to that slot is ready to be executed, dependent on whether the associated operand data is available in that slot.

9. A data processing apparatus as claimed in claim 8 , wherein said status information includes an operand status field for each slot, and the issue queue circuitry is configured to set said operand status field when the associated operand data is available within said slot.

10. A data processing apparatus as claimed in claim 5 , wherein the issue queue circuitry is configured to receive information from the execution circuitry as to the availability of each execution unit to receive at least one control data block for processing, and the issue queue circuitry determines, for each slot, whether the control data block allocated to that slot is ready to be executed, dependent on whether the execution unit capable of processing that control data block is available.

11. A data processing apparatus as claimed in claim 5 , wherein said status information comprises ordering constraint information, and the issue queue circuitry is configured to determine that the control data block allocated to a particular slot is not ready to be executed when the ordering constraint information identifies at least one other slot that contains a control data block that requires processing prior to the control data block in the particular slot.

12. A data processing apparatus as claimed in claim 5 , wherein:
the issue queue circuitry is configured to issue up to X control data blocks to the execution circuitry per issue cycle, where X is an integer greater than 0; and
the data processing apparatus further comprises issue control circuitry configured to perform an arbitration operation when the ready for execution information set by the issue queue circuitry identifies more than X slots as containing a control data block that is ready to be executed by the execution circuitry.

13. A data processing apparatus as claimed in claim 1 , further comprising:
a register file configured to store operand data; and
a forwarding path configured to directly provide, to the issue queue, result operand data generated by said execution circuitry for storage within the register file;
wherein the issue queue has operand access circuitry connected to both the register file and the forwarding path and configured to store, within each slot, the associated operand data for the control data block allocated to that slot.

14. A data processing apparatus as claimed in claim 1 , wherein:
said first operand execution unit comprises a SIMD (Single Instruction Multiple Data) execution unit configured to perform an operation in parallel on a plurality of data values;
said instruction suitable for execution by said first operand execution unit is a SIMD instruction, and each item of operand data specified by the SIMD instruction comprises multiple data values.

15. A data processing apparatus as claimed in claim 1 , wherein:
said execution circuitry is configured to execute instructions from an instruction set;
said instruction suitable for execution by said first operand execution unit is a complex instruction within said instruction set, said complex instruction specifying a sequence of operations, and said complex instruction specifying more items of operand data than are specified by at least one other instruction in said instruction set.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Airaud Cedric Denis Robert
• Scalabrino Luca
• Arsanto Frederic Jean Denis
• Schon Guillaume
• Piry Frederic Claude Marie
• Tonnerre Albin Pierick

Classifications

• G06F9/30014

  with variable precision · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/30196

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title