Modified balanced throughput data-path architecture for special correlation applications

Patent metadata

Field	Value
Publication number	US-9424033-B2
Application number	US-201313936886-A
Country	US
Kind code	B2
Filing date	Jul 8, 2013
Priority date	Jul 11, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.

First claim

We claim:

1. An apparatus for performing signal processing operations comprising:
a memory storage unit;
an Address Generator (AG) unit functionally connected to the memory storage unit and operable to receive data from, and write data to, the memory storage unit over a data bus that has a plurality of data widths;
a register file system functionally connected to the AG unit and operable to receive data from, and write data to, the AG unit, and to store data in a register memory array;
a multiply-accumulate (MAC) execution unit functionally connected to the register file system and operable to receive data from and write data to the register memory array, and which multiplies and adds pairs of data values and writes the sum to a location in the register memory array;
a multiplexer (MUX)unit functionally connected to the register file system and by a data path to the AG unit and operable to receive data from the register file system, and from the AG unit over the data bus;
wherein the register file system is organized in a hierarchical scheme for the individual register memory locations, in which pairs of individual register memory locations are organized into paired register (PR) units, and pairs of PR units are organized into group register (GR) units; and
wherein the AG unit uses a misaligned address placement (MAP) system to place data from the memory storage unit into the register file system by aligning any misaligned address with a middle point of a (GR) unit.

2. The apparatus of claim 1 wherein a plurality of widths of the data bus from the system memory storage unit to the AG unit is a positive power of 2 of a size in bytes of an individual register memory location.

3. The apparatus of claim 1 wherein the AG unit accesses the memory storage unit through a single port.

4. The apparatus of claim 1 wherein the AG unit has one address adder.

5. The apparatus of claim 1 wherein the hierarchical organization scheme organizes eight register locations into two GR units according to either a left-hand mode or a right-hand mode; wherein the left-hand mode arranges registers r 0 through r 3 into GR 0 in the order [r 1 , r 0 , r 3 , r 2 ] and the registers r 4 through r 7 into GR 1 in the order [r 5 , r 4 , r 7 , r 6 ]; and wherein the right-hand mode arranges registers r 0 through r 4 into GR 0 in the order [r 3 , r 2 , r 1 , r 0 ] and the registers r 5 through r 7 into GR 1 in the order [r 7 , r 6 , r 5 , r 4 ].

6. The apparatus of claim 5 wherein the AG unit moves data into the GR units by moving a block of data that is double a size in bytes of a standard register's size in bytes, wherein the AG unit determines an alignment point for the bytes being moved from the memory storage unit, the AG unit aligning said alignment point with the middle point of a GR unit into which the AG unit is to move the data, and the data is correspondingly loaded byte-wise into said GR unit.

7. The apparatus of claim 6 wherein the AG unit moves two blocks of data, each of a size (in bytes) double the standard register's size in bytes, by loading the first block with the GR unit first configured in the left-hand ordering, and the second block of data in the right-hand ordering.

8. The apparatus of claim 6 wherein the AG unit sequentially moves pairs of blocks of data into corresponding GR units, two blocks of data to one GR unit, by determining the appropriate alignment point for each pair of data blocks.

9. The apparatus of claim 6 wherein the MUX unit directly receives data directly from the AG unit, as well as data from the register file system, and loads the values directly into the MAC unit.

10. The apparatus of claim 9 wherein the MUX unit is configured to function without combining data from the AG unit.

11. The apparatus of claim 1 wherein the MAC execution unit is configured for single-instruction, multiple data (SIMD) operation.

12. The apparatus of claim 1 wherein the MAC execution unit is configured for a positive integer K MAC operations per cycle; wherein a size of the data values to be multiplied is a positive power of 2, M; and wherein the data path from the memory storage unit to the register memory array is 2*M*K.

13. A method for performing processing operations comprising:
reading, from a memory storage unit, a plurality of values to be used in an operation;
moving values by an Address Generator (AG) unit from and to register memory locations organized by using both a three-tier hierarchical access scheme and a misaligned address placement (MAP) process;
moving values from the register memory locations into a multiply-accumulate (MAC) execution unit;
performing the MAC operation; and
writing the result of the operation into register locations;
wherein the three-tier hierarchical access scheme organizes pairs of individual register memory locations into paired register (PR) units, and organizes pairs of PR units into group register (GR) units; and
wherein data is moved from the memory storage unit into the MAC unit by the AG unit through a multiplexing operation without being stored in the register memory locations.

14. The method of claim 13 wherein the plurality of values read from the memory storage unit is moved across a data bus by the AG unit, and wherein the data bus is configured to move double or quadruple data widths in each move.

15. The method of claim 13 wherein the three-tier hierarchical organization scheme organizes eight register locations into two GR units according to either a left-hand mode or a right-hand mode;
wherein the left-hand mode arranges registers r 0 through r 3 into GR 0 in the order [r 1 , r 0 , r 3 , r 2 ] and the registers r 4 through r 7 into GR 1 in the order [r 5 , r 4 , r 7 , r 6 ]; and
wherein the right-hand mode arranges registers r 0 through r 4 into GR 0 in the order [r 3 , r 2 , r 1 , r 0 ] and the registers r 5 through r 7 into GR 1 in the order [r 7 , r 6 , r 5 , r 4 ].

16. The method of claim 13 wherein the AG unit moves data into the GR units by moving a block of data that is double the size in bytes of a standard register's size in bytes, by the AG unit determining an alignment point of the bytes being moved from memory storage unit, the AG unit aligning said alignment point with the middle point of a GR unit into which the AG unit is to move the data, and the data is correspondingly loaded byte-wise into said GR unit.

17. The method of claim 16 wherein the AG unit moves two blocks of data, each of size double the standard register's size, by loading the first block first with the group register configured in the left-hand ordering, and the second block of data in the right-hand ordering.

18. The method of claim 16 wherein the AG unit sequentially moves a plurality of pairs of blocks of data into corresponding GR units, two blocks of data to one GR unit, by determining the appropriate alignment point for each pair of data blocks.

19. The method of claim 13 wherein the MAC execution unit performs single-instruction, multiple data (SIMD) operations.

20. The method of claim 19 wherein the MAC execution unit operates by performing positive integer K SIMD operations per cycle; wherein the size of the data values to be multiplied is a positive power of 2, M; and wherein the data path from the memory storage unit to the register memory array is 2*M*K.

Assignees

• Stmicroelectronics (Beijing) R&D Company Ltd
• St Microelectronics Srl

Inventors

• Zhu Pengfei
• Sun Hongxia
• Wu Yongqiang
• Guidetti Elio

Classifications

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/3893

  controlled in tandem, e.g. multiplier-accumulator · CPC title

• G06F9/30127

  Register windows · CPC title