Control of Memory Access Cycles for Thermal Stability and Performance
US-2024370175-A1 · Nov 7, 2024 · US
US9423970B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9423970-B2 |
| Application number | US-201314144195-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 30, 2013 |
| Priority date | Dec 30, 2013 |
| Publication date | Aug 23, 2016 |
| Grant date | Aug 23, 2016 |
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A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative erase cycle at which the erase time threshold is exceeded are assumed to have a greater erase cycle life than those that need to exceed the erase time threshold at an earlier erase cycle. This information is used to adjust wear leveling in the form of free block selection, garbage collection block selection and other block management processes. Alternatively or in combination, the predicted erase cycle life information is used to adjust program and/or erase parameters such as erase voltage and time.
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I claim: 1. An apparatus comprising: a plurality of blocks of non-volatile memory cells, each of the plurality of blocks comprising a plurality of the non-volatile memory cells; and a controller in communication with the plurality of blocks, wherein the controller is configured to: monitor a time duration for erasing one or more of the plurality of blocks; identify a time, for each of the one or more of the plurality of blocks, when the time duration exceeds a predetermined t…
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