Method and system for predicting block failure in a non-volatile memory

US9423970B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9423970-B2
Application numberUS-201314144195-A
CountryUS
Kind codeB2
Filing dateDec 30, 2013
Priority dateDec 30, 2013
Publication dateAug 23, 2016
Grant dateAug 23, 2016

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Abstract

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A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative erase cycle at which the erase time threshold is exceeded are assumed to have a greater erase cycle life than those that need to exceed the erase time threshold at an earlier erase cycle. This information is used to adjust wear leveling in the form of free block selection, garbage collection block selection and other block management processes. Alternatively or in combination, the predicted erase cycle life information is used to adjust program and/or erase parameters such as erase voltage and time.

First claim

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I claim: 1. An apparatus comprising: a plurality of blocks of non-volatile memory cells, each of the plurality of blocks comprising a plurality of the non-volatile memory cells; and a controller in communication with the plurality of blocks, wherein the controller is configured to: monitor a time duration for erasing one or more of the plurality of blocks; identify a time, for each of the one or more of the plurality of blocks, when the time duration exceeds a predetermined t…

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What does patent US9423970B2 cover?
A method and system are disclosed for improved block erase cycle life prediction and block management in a non-volatile memory. The method includes the storage device tracking information relating to a first erase cycle count at which the block erase time exceeded a predetermined threshold relative to a first erase cycle at which this occurred in other blocks. Blocks having a later relative era…
Who is the assignee on this patent?
Sandisk Technologies Inc, Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification G06F3/0616. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).