Inductive charge balancing

Patent metadata

Field	Value
Publication number	US-9423450-B2
Application number	US-201414339696-A
Country	US
Kind code	B2
Filing date	Jul 24, 2014
Priority date	Jan 31, 2011
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Disclosed is a method for charge balancing in a charge storage arrangement having a plurality of charge storage cells connected in series, and a charge balancing circuit.

First claim

What is claimed is:

1. A method for charge balancing in a charge storage arrangement having a plurality of charge storage cells connected in series, a first inductive storage element configured to be selectively coupled with the charge storage arrangement, and at least one second inductive storage element configured to be selectively coupled with a first one of the plurality of charge storage cells and inductively coupled to the first inductive storage element, the method comprising:
during a first time period, taking energy from one of the charge storage arrangement or the first one of the plurality of charge storage cells by coupling the associated inductive storage element with the charge storage arrangement or the first one of the plurality of charge storage cells, respectively;
during a second time period subsequent to the first time period, feeding back at least a part of the taken energy into the other one of the charge storage arrangement or the first one of the plurality of charge storage cells by coupling an associated inductive storage element with the other one of the charge storage arrangement or the first one of the plurality of charge storage cells, respectively;
evaluating at least one of a first voltage and/or a second voltage at least at one time in the first time period to provide a first evaluation result and at least at one time in the second time period to provide a second evaluation result, wherein the first voltage is dependent on a voltage across the first inductive storage element and the second voltage is dependent on a voltage across the at least one second inductive storage element; and
detecting a fault in circuitry coupled to the charge storage cells based on the first and the second evaluation result.

2. The method of claim 1 , wherein the first voltage is a voltage across the first inductive storage element.

3. The method of claim 1 , wherein the first voltage corresponds to a difference between a voltage across the charge storage arrangement and a voltage across the first inductive storage element.

4. The method of claim 1 , wherein the second voltage is the voltage across at least one second inductive storage element.

5. The method of claim 1 , wherein evaluating the first voltage comprises comparing the first voltage with at least one reference value to obtain a first comparison signal, wherein a fault is detected when the first comparison signal does not change between the first time period and the second time period.

6. The method of claim 1 , further comprising:
comparing the first voltage with a first reference value to obtain a first comparison signal; and
comparing the second voltage with a second reference value to obtain a second comparison signal,
wherein a fault is detected when at least one of the first and second comparison signals does not change between the first time period and the second time period.

7. The method of claim 1 , wherein evaluating the second voltage comprises comparing the second voltage with at least one further reference value to obtain a further comparison signal, wherein a fault is detected, when the further comparison signal does not change between the first time period and the second time period.

8. The method of claim 7 , further comprising:
comparing the second voltage with a third reference value to obtain a third comparison signal; and
comparing the second voltage with a fourth reference value to obtain a fourth comparison signal,
wherein a fault is detected when at least one of the third and fourth comparison signals does not change between the first time period and the second time period.

9. The method of claim 1 , wherein evaluating the first and second voltages comprises:
comparing the first voltage with at least one of a first reference voltage and a second reference voltage to obtain at least one of a first comparison signal and a second comparison signal; and
comparing the second voltage with at least one of a third reference voltage and a fourth reference voltage to obtain at least one of a third comparison signal and a fourth comparison signal,
wherein a fault is detected when one of the first and second comparison signals and one of the third and fourth comparison signals do not change between the first time period and the second time period.

10. The method of claim 9 , which comprises a sequence of balancing cycles, with each balancing cycle including a first time period and a subsequent second time period, the method further comprising:
evaluating at least one of the first, second, third and fourth comparison signal; and
starting a new balancing cycle dependent on at least one of the first evaluation result and the second evaluation result.

11. The method of claim 10 , wherein a new balancing cycle is started after a predetermined edge of the at least one of the comparison signals.

12. The method of claim 11 , wherein a new balancing cycle is started after a predetermined edge of the first and third comparison signals.

13. The method of claim 11 , wherein a new balancing cycle is started after a predetermined edge of the second and fourth comparison signals.

14. A charge balancing circuit, comprising:
a drive circuit configured to be coupled to a first inductive storage element, at least one second inductive storage element, and a storage arrangement comprising a plurality of storage cells connected in series, the drive circuit configured to
cause one of the first inductive storage element or the second inductive storage element to be coupled with the storage arrangement or a first one of the plurality of storage cells for a first time period, and
cause the other one of the first inductive storage element or the second inductive storage element to be coupled with the storage arrangement or first one of the plurality of storage cells for a second time period subsequent to the first time period; and

an error detection circuit configured to
evaluate at least one of a first voltage and a second voltage at least at one time in the first time period to obtain a first evaluation result and at least at one time in the second time period to obtain a second evaluation result, wherein the first voltage is dependent on a voltage across the first inductive storage element and the second voltage is dependent on a voltage across the at least one second inductive storage element, and
generate an error signal dependent on the first and the second evaluation results, wherein the error signal indicates a fault in circuitry coupled to the storage arrangement.

15. The charge balancing circuit of claim 14 , further comprising:
a first switching element coupled in series with the first inductive storage element, controlled by the drive circuit and configured to couple the first inductive storage element to the storage arrangement; and
at least one second switching element coupled in series with the at least one second inductive storage element, controlled by the drive circuit and configured to couple the at least one second inductive storage element to the first one of the plurality of storage cells.

16. The charge balancing circuit of claim 14 , wherein the first voltage is the voltage across the first inductive storage element.

17. The charge balancing circuit of claim 14 , wherein the first voltage corresponds to a difference between a voltage across the storage arrangement and the voltage across the first inductive storage element.

18. The charge balancing circuit of claim 14 , wherein the second voltage is the voltage across the at least one second inductive sto

Assignees

• Infineon Technologies Ag

Inventors

• Kain Clemens

Classifications

• H02J7/54

  Passive balancing, e.g. using resistors or parallel MOSFETs · CPC title

• H02J7/52

  for charge balancing, e.g. equalisation of charge between batteries · CPC title

• H02J2207/20

  Charging or discharging characterised by the power electronics converter · CPC title

• H02J7/0016

  Electricity · mapped topic

• Y02T10/7055

  Cross-Sectional Technologies · mapped topic