Integrated circuit having receiver jitter tolerance (“JTOL”) measurement

Patent metadata

Field	Value
Publication number	US-9423441-B2
Application number	US-201213621783-A
Country	US
Kind code	B2
Filing date	Sep 17, 2012
Priority date	Mar 20, 2007
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

First claim

What is claimed is:

1. An integrated circuit, comprising:
circuitry to sample an input signal according to a sampling clock, to generate data samples;
a clock source to generate the sampling clock;
circuitry to compare expected data values with the data samples and to generate an error indication in dependence on whether the expected data values match the data samples; and
circuitry to inject jitter into the sampling clock to simulate jitter in the input signal;
wherein the clock source comprises a clock recovery circuit operable to generate a recovered clock in dependence on transitions in the input signal, the sampling clock being dependent on the recovered clock.

2. The integrated circuit of claim 1 , where:
the integrated circuit further comprises a mode register; and
the circuitry to inject jitter is controlled responsive to content of the mode register so as to inject jitter into the recovered clock in a first mode but not in a second mode.

3. The integrated circuit of 1 , where the circuitry to inject jitter is operable to inject at least one of sinusoidal jitter (Si), random jitter (RJ) and deterministic jitter (DJ).

4. The integrated circuit of claim 1 , embodied as a field programmable logic array (FPGA).

5. The integrated circuit of claim 1 , further comprising storage to store the expected data, the circuitry to compare operable to obtain the expected data from the storage.

6. The integrated circuit of claim 1 , where:
the clock recovery circuit comprises a summing junction and at least one of a phase accumulator and a frequency accumulator coupled to the summing junction;
the circuitry to inject jitter is to inject the jitter into the summing junction; and
the recovered clock is to be generated in dependence on an output of the summing junction.

7. The integrated circuit of claim 6 , where the at least one of the phase accumulator and the frequency accumulator is coupled to receive an output of the summing junction.

8. The integrated circuit of claim 6 , where the at least one includes both of a phase accumulator and a frequency accumulator, each of the phase accumulator and the frequency accumulator coupled to the summing junction.

9. The integrated circuit of claim 6 , where the clock recovery circuit further comprises a phase interpolator coupled to receive the output of the summing junction, the output of the summing junction to control phase of an output produced by the phase interpolator.

10. The integrated circuit of claim 1 , further comprising circuitry to generate a control signal to control amount of jitter to be injected into the sampling clock.

11. The integrated circuit of claim 10 , where the circuitry to generate the control signal comprises a pseudorandom bit sequence (PRBS) generator and where the circuitry to generate the control signal is to generate the control signal as a PRBS signal, to inject pseudorandom jitter into the PRBS signal.

12. The integrated circuit of claim 10 , where the circuitry to generate the control signal comprises a modulation source to generate a repeating pattern, the circuitry to generate the control signal operable to generate the control signal in dependence on the repeating pattern.

13. The integrated circuit of claim 10 , where the circuitry to generate the control signal comprises storage to store a pattern, the circuitry to generate the control signal operable to generate the control signal in dependence on the pattern.

14. The integrated circuit of claim 13 , where the circuitry to generate the control signal comprises storage that is programmable externally from the integrated circuit, the circuitry to generate the control signal in dependence on at least one programmable value stored in the storage.

15. The integrated circuit of claim 1 , further comprising a pattern generator operable to generate the expected data, the circuitry to compare coupled to the pattern generator to obtain the expected data from the pattern generator.

16. The integrated circuit of claim 15 , where the pattern generator is a self-seeded PRBS generator.

17. An integrated circuit comprising:
a receiver to sample an input signal to the integrated circuit to generate data samples; and
a clock recovery circuit to generate a recovered clock;
wherein
the receiver is to sample the input signal in dependence on the recovered clock,
the integrated circuit is to operate in a first mode in which the clock recovery circuit generates the recovered clock in dependence on transitions in the input signal and a control signal, the control signal representing noise to be injected into the recovered clock, such that the recovered clock experiences time-varying offset relative to transitions in the input signal, and
the integrated circuit is also to operate in a second mode in which the clock recovery circuit generates the recovered clock in dependence on the transitions in the input signal but not in dependence on the control signal;
where the integrated circuit further comprises circuitry to in the first mode compare expected data values with the data samples and to generate an error indication in dependence on whether the expected data values match the data samples.

18. A method of testing jitter tolerance of an integrated circuit in receiving a data-conveying input signal, comprising:
recovering a clock embedded in the data-conveying input signal using logic level transitions in the data-conveying input signal;
using a data clock in each of a first mode and a second mode to sample the input signal, the data clock dependent on the recovered clock; and
in the first mode but not the second mode,
injecting a controlled amount of jitter into the data clock to generate a noisy data clock,
using the noisy data clock to sample the input signal to generate samples, and
comparing the samples with expected data to detect errors in the samples.

19. The method of claim 18 , where the integrated circuit further comprises a clock recovery circuit (CDR) and the method further comprises in the first mode, using the CDR to generate the data clock in dependence on transitions in the input signal and in dependence on stored control information operable to define the controlled amount of jitter and, in the second mode using the CDR to generate the data clock in a manner not dependent on the stored controlled information.

20. The method of claim 18 , embodied at least in part as instructions stored on machine-readable media.

21. The method of claim 18 , where the integrated circuit further comprises a pseudorandom bit sequence (PRBS) generator, where the method further comprises determining whether the integrated circuit passes a jitter tolerance (JTOL) metric for jitter potentially present in the input signal dependent on errors detected in the first mode, and where the input signal in the first mode is uncorrelated with the controlled amount of jitter.

22. An integrated circuit, comprising:
a receive circuit to sample an input signal according to a sampling clock to generate data samples;
circuitry to generate the sampling clock;
circuitry to generate a signal representing jitter;
where the integrated circuit has a first mode, in which the circuitry to generate the sampling clock is to generate the sampling clock in dependence on the signal representing jitter, and a second mode, in which the circuitry to generate the sampling clock is to generate the sampling clock not in dependence on the signal representing jitter;
a pseudorandom bit

Assignees

• Lee Hae-Chang
• Kim Jaeha
• Leibowitz Brian
• Rambus Inc

Inventors

• Lee Hae-Chang
• Kim Jaeha
• Leibowitz Brian

Classifications

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/31709 Primary

  Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901) · CPC title

• G01R29/26 Primary

  Measuring noise figure; Measuring signal-to-noise ratio · CPC title