Test device and test method for measuring a phase noise of a test signal

Patent metadata

Field	Value
Publication number	US-9423440-B2
Application number	US-200913502099-A
Country	US
Kind code	B2
Filing date	Oct 21, 2009
Priority date	Oct 21, 2009
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A test device for measuring a phase noise of a test signal includes a delayer configured to delay the test signal to provide a delayed test signal, a first combiner, a second combiner, and a phase noise determinator. The first combiner is configured to combine a first signal with the delayed test signal to provide a first combiner output signal. The first signal is based on the test signal or a signal identical to the test signal. The second combiner is configured to combine a second signal with the delayed test signal, wherein the second signal is phase-shifted with respect to the first signal to provide a second combiner output signal. The second signal is based on the test signal. The phase noise determinator is configured to provide phase noise information that depends on the first combiner output signal and the second combiner output signal.

First claim

What is claimed is:

1. A test device for measuring phase noise of a test signal, the test device comprising:
a delayer that delays the test signal to provide a delayed test signal; wherein the delayer comprises a recursive delayer to recursively delay the test signal to provide the delayed test signal and to form an additive superposition of the test signal and the delayed test signal to provide a superposed signal, wherein the recursive delayer attenuates and delays the superposed signal to provide the delayed test signal;
a first combiner that combines a first signal with the delayed test signal to obtain a first combiner output signal, wherein the first signal is based on one of the test signal and a signal identical to the test signal;
a second combiner that combines a second signal with the delayed test signal to provide a second combiner output signal, wherein the second signal is based on the test signal, and wherein the second signal is phase-shifted with respect to the first signal;
a phase noise determinator that determines phase noise information based on the first combiner output signal and the second combiner output signal.

2. The test device according to claim 1 , wherein the phase noise determinator is further configured to combine the first combiner output signal and the second combiner output signal to determine the phase noise information.

3. The test device according to claim 1 , wherein the phase noise information comprises a power spectral distribution.

4. The test device according to claim 3 , wherein the phase noise determinator is further configured to additively superpose a signal representing a power of the first combiner output signal and a signal representing a power of the second combiner output signal to determine information describing a power of the phase noise.

5. The test device according to claim 4 , wherein the phase noise determinator is configured to use a frequency dependent term (1-cos(2πfT d )) when determining the power of the phase noise information depending on the additive superposition of the powers of the first combiner output signal and the second combiner output signal, wherein f designates a frequency of the phase noise and T d designates a delay time by which the delayed test signal is delayed with respect to the test signal.

6. The test device according to claim 5 , wherein the delayer is configured to delay the test signal by a delay time T d , wherein the phase noise transmission factor H(f) amplifies the phase noise such that the phase noise is detectable from background noise.

7. The test device according to claim 5 , wherein the delayer is configured to delay the test signal by a delay time T d , the delay time T d not deviating by more than 50 percent from a time value 1/(2f max ), wherein f max designates a predetermined maximum offset-frequency of interest of the phase noise.

8. The test device according to claim 1 , wherein the phase noise determinator is further configured to determine a power of the phase noise information depending on a phase noise transmission factor, and wherein the phase noise transmission factor depends on a frequency of the phase noise information and on a delay time by which the delayed test signal is delayed with respect to the test signal.

9. The test device according to claim 1 , wherein a carrier of the first signal and a carrier of the second signal are in phase quadrature within a tolerance range of +/−10 degrees.

10. The test device according to claim 1 , wherein a phase shift between the first signal and the delayed test signal deviates from a phase quadrature condition by more than 10°, and wherein a phase shift between the second signal and the delayed test signal deviates from a phase quadrature condition by more than 10°.

11. The test device according to claim 1 , wherein the first combiner is further configured to multiply the first signal with the delayed test signal to determine the first combiner output signal, and wherein the second combiner is further configured to multiply the second signal with the delayed test signal to determine the second combiner output signal.

12. The test device according to claim 1 , wherein the delayer is configured to shift the test signal in time, wherein a time shift for frequencies of the test signal surrounding a carrier frequency of the test signal within a range of +/−20% around the carrier frequency is frequency-independent.

13. The test device according to claim 1 , wherein the delayer comprises:
a transmission line;
a transmission line of adjustable length;
an amplifier;
a plurality of amplifiers connected in series; and
a plurality of switchable amplifiers connected in series.

14. The test device according to claim 1 , further comprising a phase shifter configured to shift the phase of the test signal to obtain the first signal or the second signal.

15. The test device according to claim 14 , wherein the phase shifter is configured to offset a phase shift between the first signal and the second signal, wherein the first signal and the second signal are in a phase quadrature within a tolerance range of +/−10°.

16. The test device according to claim 15 , wherein the phase shifter is configured to shift a phase of the test signal, wherein the phase-shift for frequencies of the test signal surrounding a carrier frequency of the test signal within a range of +/−20% around the carrier frequency is frequency-independent.

17. The test device according to claim 14 , wherein the phase shifter comprises one of:
a passive RC-circuit comprising a plurality of resistors and a plurality of capacitors, wherein the pluralities of resistors and capacitors are electrically connected, and wherein the phase shifter shifts the phase of the test signal by a predetermined value; and
an active RC-circuit comprising a plurality of operational amplifiers or transistors, a plurality of resistors and a plurality of capacitors, wherein the pluralities of operational amplifiers or transistors, resistors, and capacitors are electrically connected, and wherein the phase shifter shifts the phase of the test signal by a predetermined value.

18. The test device as claimed in claim 14 , wherein the phase-shifted test signal is phase-shifted with respect to the first signal by a phase-shift of 90° or by 90° plus an integer multiple of 180°.

19. The test device according to claim 1 , wherein the phase noise determinator comprises a first low-pass filter configured to filter the first combiner output signal to provide a first low-pass filter output signal, and a second low-pass filter configured to filter the second combiner output signal to provide a second low-pass filter output signal.

20. The test device according to claim 1 , wherein the phase noise determinator comprises:
a first analog-to-digital converter configured to analog-to-digital convert the first low-pass filter output signal; and
a second analog-to-digital converter configured to analog-to-digital convert the second low-pass filter output signal.

21. The test device according to claim 1 , wherein the test device comprises a receiver configured to receive a radio frequency signal in the range of 1 GHz to 10 GHz.

22. The test device according to claim 1 further comprising:
an adder configured to form the additive superposition of the test signal and the delayed test signal; and
an attenuator and a second delayer configured to attenuate and delay the superposed signal to provide the delayed test signa

Assignees

• Pausini Marco
• Advantest Corp

Inventors

• Pausini Marco

Classifications

• G01R31/31709

  Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901) · CPC title

• G01R29/26 Primary

  Measuring noise figure; Measuring signal-to-noise ratio · CPC title