Electronic power device and method of fabricating an electronic power device

Patent metadata

Field	Value
Publication number	US-9420731-B2
Application number	US-201314030433-A
Country	US
Kind code	B2
Filing date	Sep 18, 2013
Priority date	Sep 18, 2013
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An electronic device comprises a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is configured as a heat dissipating surface without electrical power terminal functionality. The electronic device comprises a porous metal layer arranged on the portion of the first main surface.

First claim

What is claimed is:

1. An electronic device, comprising:
a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is a heat dissipating surface without electrical power terminal functionality;
a first porous metal layer arranged on the portion of the first main surface;
a chip carrier; and
a power semiconductor chip mounted on the chip carrier, wherein the chip carrier is exposed at the portion of the first main surface of the power module,
wherein the chip carrier comprises a metal bonded ceramic substrate or a leadframe.

2. electronic device of claim 1 , further comprising:
a second porous metal layer arranged on a portion of the second main surface, wherein at least the portion of the second main surface is a heat dissipating surface without electrical power terminal functionality.

3. The electronic device of claim 1 , wherein the first porous metal layer comprises a metal selected from the group consisting of Cu, Al, Ag, Ni. Mo and alloys thereof.

4. The electronic device of claim 1 , wherein the first porous metal layer comprises a thickness in a range from 20 μm to 200 μm.

5. The electronic device of claim 1 , wherein the first porous metal layer comprises a porosity in a range from 20% to 90%.

6. The electronic device of claim 1 , wherein the first porous metal layer comprises a thermal conductivity of equal to or greater than 10 W/(mK).

7. The electronic device of claim 1 , wherein the first porous metal layer is an open-celled metal foam layer.

8. The electronic device of claim 1 , wherein the first porous metal layer is a particle layer comprising particles having a mean particle size in a range from 1 μm to 20 μm.

9. The electronic device of claim 1 , wherein the first porous metal layer is configured to deform when the electronic device is clamped with the first porous metal layer t0 a first heat sink.

10. The electronic device of claim 1 , further comprising:
an insulating layer extending between the power semiconductor chip and the first porous metal layer.

11. The electronic device of claim 1 , further comprising:
a second chip carrier exposed at the second main surface of the power module.

12. An electronic device, comprising:
a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is a heat dissipating surface without electrical power terminal functionality;
a first porous metal layer arranged on the portion of the first main surface; and
a second porous metal layer arranged on a portion of the second main surface,
wherein at least the portion of the second main surface is a heat dissipating surface without electrical power terminal functionality, and
wherein the first and second metal porous layers are completely separated from one another.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Hosseini Khalil
• Mahler Joachim
• Nikitin Ivan

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/07331

  Connecting techniques · CPC title