Key management using security enclave processor

Patent metadata

Field	Value
Publication number	US-9419794-B2
Application number	US-201414493458-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Sep 25, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

First claim

What is claimed is:

1. An integrated circuit comprising:
a processor;
a security circuit coupled to the processor, wherein the security circuit comprises an encryption circuit that is configured to generate a first key using a first local key and to encrypt the first key using a second local key to generate a second key, and wherein the encryption circuit is configured to generate the first local key and the second local key during initialization of the security circuit, wherein the security circuit is configured to provide the second key to the processor in response to a read by the processor, wherein the security circuit comprises a first software-accessible register, and wherein the security circuit is configured to write the second key to the first software-accessible register to provide the second key in response to the read by the processor, and wherein the processor is configured to generate a read operation to the first software-accessible register to receive the second key from the security circuit; and
a first encryption peripheral external to the security circuit, wherein the first encryption peripheral is coupled to the security circuit and is configured to receive the second local key from the security circuit via hardware transmission from the security circuit, wherein the second local key is stored in one or more registers of the security circuit that are not software accessible, and wherein the first encryption peripheral is coupled to the processor and is configured to receive the second key from the processor, and wherein the first encryption peripheral is configured to decrypt the second key responsive to the second local key, and wherein the first encryption peripheral is configured to use the first key resulting from decrypting the second key for encryption operations, wherein the first encryption peripheral includes a second software-accessible register, and wherein the processor is configured to generate a write operation subsequent to reading the second key from the security circuit, the write operation writing the second key to the second software-accessible register, wherein the security circuit is configured to receive an instance-specific value and is configured to generate the first local key responsive to the instance specific value and at least one instance-invariant value.

2. The integrated circuit as recited in claim 1 wherein the processor is configured to generate the read operation and the write operation responsive to instructions executed by the processor during use.

3. The integrated circuit as recited in claim 1 further comprising a plurality of encryption peripherals including the first encryption peripheral, wherein each of the plurality of encryption peripherals is coupled to receive the second local key from the security circuit via hardware transmission.

4. The integrated circuit as recited in claim 1 wherein the instance-specific value is provided from a plurality of fuses in the integrated circuit.

5. The integrated circuit as recited in claim 1 wherein the instance-invariant value is a seed specified for the integrated circuit.

6. A method comprising:
during initialization of a security circuit, generating a first local key and a second local key in an encryption circuit in the security circuit, wherein the security circuit is coupled to a processor and a first encryption peripheral, and wherein the first encryption circuit is external to the security circuit;
generating a first key using the first local key in the encryption circuit;
encrypting the first key using a second local key in the encryption circuit to generate a second key;
writing the second key to a first software-accessible register in the security circuit; and
generating a read operation to the first software-accessible register from the processor to receive the second key from the security circuit; and
providing the second key to the processor in response to a read by the processor of the first software-accessible register;
receiving the second local key in the first encryption peripheral from the security circuit via hardware transmission from the security circuit, wherein the second local key is stored in one or more registers of the security circuit that are not software accessible;
generating a write operation by the processor subsequent to reading the second key from the security circuit, the write operation writing the second key to a second software-accessible register in the first encryption peripheral;
receiving the second key from the processor in the second software-accessible register in the first encryption peripheral;
decrypting the second key in the first encryption peripheral responsive to the second local key;
using the first key resulting from decrypting the second key in the first encryption peripheral for encryption operations in the first encryption peripheral;
receiving an instance-specific value in the security circuit; and
generating the first local key responsive to the instance specific value and at least one instance-invariant value.

7. The method as recited in claim 6 further comprising:
generating the read operation and the write operation responsive to instructions executed by the processor.

8. The method as recited in claim 6 wherein the system further comprises a plurality of encryption peripherals including the first encryption peripheral, and the method further comprising each of the plurality of encryption peripherals receiving the second local key from the security circuit via hardware transmission.

9. The method as recited in claim 6 wherein the instance-specific value is provided from a plurality of fuses in the integrated circuit.

10. The method as recited in claim 6 wherein the instance-invariant value is a seed specified for the integrated circuit.

Assignees

• Apple Inc

Inventors

• Polzin R Stephen
• Gautier Fabrice L
• Adler Mitchell D
• Sauerwald Conrad
• Brouwer Michael L H

Classifications

• H04L9/0822

  using key encryption key · CPC title

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title

• H04L9/0897

  involving additional devices, e.g. trusted platform module [TPM], smartcard or USB · CPC title

• G09C1/00 Primary

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/0861 Primary

  Generation of secret information including derivation or calculation of cryptographic keys or passwords · CPC title