Non-polynomial processing unit for soft-decision error correction coding

Patent metadata

Field	Value
Publication number	US-9419651-B2
Application number	US-65138609-A
Country	US
Kind code	B2
Filing date	Dec 31, 2009
Priority date	Dec 31, 2008
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

First claim

What is claimed is:

1. An error-correcting module comprising:
error correction circuitry configured to
receive soft-decision data about a stream of bits, the soft-decision data indicative of potential bit errors and comprising an error polynomial and an auxiliary polynomial,
calculate a gradient polynomial based upon a gradient between the error polynomial and the auxiliary polynomial,
determine a number of errors in the stream of bits by determining a number of roots in the error polynomial without determining coefficients of the error polynomial,
when the determined number of errors is greater than an error-correction capacity, iteratively changing the stream of bits, and iteratively determining a new number of errors in the changed stream of bits based upon only an updated gradient polynomial, and
when the determined number of errors is less than the error-correction capacity, send the stream of bits for error-correction.

2. The error-correcting module of claim 1 wherein said error correction circuitry is configured to manipulate the soft decision data by at least changing at least one bit of data from a current logic state to a different logic state.

3. The error-correcting module of claim 1 wherein said error correction circuitry is configured to manipulate the soft decision data by at least iteratively changing a series of bits of data according to a grey code schema.

4. The error-correcting module of claim 1 wherein the error correction circuitry is configured to determine a number of errors in the stream of bits based upon determining a difference between a first finite field and a second finite field, each finite field defined by the soft-decision data.

5. The error-correcting module of claim 1 wherein the error polynomial and the auxiliary polynomial define a plurality of polynomials; and wherein the error correction circuitry is configured to:
evaluate the plurality of polynomials using bit locations identified as a flip location; and
evaluate the plurality of polynomials differently using bit locations identified as non-flip locations.

6. The error-correcting module of claim 1 wherein the error polynomial, the auxiliary polynomial, and the gradient polynomial are derived from a sector of data coded as a Reed-Solomon code.

7. A controller comprising:
a buffer manager; and
an error control circuit coupled to said buffer manager and configured to
receive soft-decision data about a stream of bits, the soft-decision data indicative of potential bit errors and comprising an error polynomial and an auxiliary polynomial,
calculate a gradient polynomial based upon a gradient between the error polynomial and the auxiliary polynomial,
determine a number of errors in the stream of bits by determining a number of roots in the error polynomial without determining coefficients of the error polynomial,
when the determined number of errors is greater than an error-correction capacity, iteratively changing the stream of bits, and iteratively determining a new number of errors in the changed stream of bits based upon only an updated gradient polynomial, and
when the determined number of errors is less than the error-correction capacity, send the stream of bits for error-correction.

8. The controller of claim 7 wherein said buffer manager and said error control circuit are carried by a single integrated circuit.

9. The controller of claim 7 wherein said buffer manager and said error control circuit are carried by separate integrated circuits.

10. The controller of claim 7 wherein said error control circuit is configured to manipulate the soft decision data by at least changing at least one bit of data from a current logic state to a different logic state.

11. The controller of claim 7 wherein said error control circuit is configured to manipulate the soft decision data by at least iteratively changing a series of bits of data according to a grey code schema.

12. The controller of claim 7 wherein the error control circuit is configured to determine a number of errors in the stream of bits based upon determining a difference between a first finite field and a second finite field, each finite field defined by the soft-decision data.

13. A hard-disk drive system comprising:
a storage medium;
a read head configured to read data from the storage medium; and
an error-code correction module configured to
receive soft-decision data about a stream of bits from said read head, the soft-decision data indicative of potential bit errors and comprising an error polynomial and an auxiliary polynomial,
calculate a gradient polynomial based upon a gradient between the error polynomial and the auxiliary polynomial,
determine a number of errors in the stream of bits by determining a number of roots in the error polynomial without determining coefficients of the error polynomial,
when the determined number of errors is greater than an error-correction capacity, iteratively changing the stream of bits, and iteratively determining a new number of errors in the changed stream of bits based upon only an updated gradient polynomial, and
when the determined number of errors is less than the error-correction capacity, send the stream of bits for error-correction.

14. The hard-disk drive system of claim 13 wherein said error-code correction module is configured to manipulate the soft decision data by at least changing at least one bit of data from a current logic state to a different logic state.

15. The hard-disk drive system of claim 13 wherein said error-code correction module is configured to manipulate the soft decision data by at least iteratively changing a series of bits of data according to a grey code schema.

16. The hard-disk drive system of claim 13 wherein the error-code correction module is configured to determine a number of errors in the stream of bits based upon determining a difference between a first finite field and a second finite field, each finite field defined by the soft-decision data.

17. A computer system comprising:
a processor; and
a hard-disk drive system coupled to said processor and comprising
a storage medium,
a read head configured to read data from the storage medium, and
an error-code correction module configured to
receive soft-decision data about a stream of bits from said read head, the soft-decision data indicative of potential bit errors and comprising an error polynomial and an auxiliary polynomial,
calculate a gradient polynomial based upon a gradient between the error polynomial and the auxiliary polynomial,
determine a number of errors in the stream of bits by determining a number of roots in the error polynomial without determining coefficients of the error polynomial,
when the determined number of errors is greater than an error-correction capacity, iteratively changing the stream of bits, and iteratively determining a new number of errors in the changed stream of bits based upon only an updated gradient polynomial, and
when the determined number of errors is less than the error-correction capacity, send the stream of bits for error-correction.

18. The computer system of claim 17 wherein said error-code correction module is configured to manipulate the soft decision data by at least changing at least one bit of data from a current logic state to a different logic state.

19. The computer system of claim 17 wherein said error-code correction module is configured to manipulate the soft decision data by at least iteratively changing a series of bits of data according to a

Assignees

• Karabed Razmik
• Ozdemir Hakan C
• Ashe Vincent Brendan
• Barndt Richard
• St Microelectronics Inc

Inventors

• Karabed Razmik
• Ozdemir Hakan C
• Ashe Vincent Brendan
• Barndt Richard

Classifications

• H03M13/373

  with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes · CPC title

• H03M13/451

  using a set of candidate code words, e.g. ordered statistics decoding [OSD] · CPC title

• G11B20/1833

  by adding special lists or symbols to the coded information (G11B20/1806, G11B20/1866 take precedence) · CPC title

• G11B2020/1836

  using a Reed Solomon [RS] code · CPC title

• H03M13/1515 Primary

  Reed-Solomon codes · CPC title