Delta sigma modulator

Patent metadata

Field	Value
Publication number	US-9419643-B2
Application number	US-201514943401-A
Country	US
Kind code	B2
Filing date	Nov 17, 2015
Priority date	Nov 26, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A ΔΣ modulator converts an input analog quantity into a digital value quantized with a predetermined number of bits and outputs the digital value. The ΔΣ modulator includes an integrator that includes a capacitor and integrates a difference between the input analog quantity and an analog quantity acquired from D/A conversion of the output digital value by a D/A converter; a quantizer that quantizes an analog quantity acquired from integration by the integrator; and a digital integrator that carries out an integration operation on data acquired from quantization by the quantizer.

First claim

What is claimed is:

1. A ΔΣ modulator converting an input analog quantity into a digital value quantized with a predetermined number of bits and outputting the digital value, the ΔΣ modulator comprising:
an integrator that includes an integration capacitor and integrates a difference between the input analog quantity and an analog quantity acquired from D/A conversion of the output digital value by a D/A converter, an end of the integration capacitor from which charge that is input from the integrator's input terminal is stored being used as the integrator's output terminal;
a quantizer that quantizes an analog quantity acquired from integration by the integrator; and
a digital integrator that carries out an integration operation on data acquired from quantization by the quantizer.

2. The ΔΣ modulator as claimed in claim 1 , further comprising:
a feedforward path provided on a signal path from an input side to an output side of the ΔΣ modulator, the feedforward path bypassing the digital integrator.

3. The ΔΣ modulator as claimed in claim 1 , further comprising:
a feedback path that returns the output digital value to an input side of the digital integrator.

4. The ΔΣ modulator as claimed in claim 1 , further comprising:
a dither signal application part that applies a dither signal to data acquired from quantization by the quantizer, the dither signal having a periodically repeated digital value of binary or more and having an amplitude greater than or equal to ½ a quantization step width of the quantizer.

5. The ΔΣ modulator as claimed in claim 2 , further comprising:
a dither signal application part that applies a dither signal to data acquired from quantization by the quantizer, the dither signal having a periodically repeated digital value of binary or more and having an amplitude greater than or equal to ½ a quantization step width of the quantizer.

6. The ΔΣ modulator as claimed in claim 3 , further comprising:
a dither signal application part that applies a dither signal to data acquired from quantization by the quantizer, the dither signal having a periodically repeated digital value of binary or more and having an amplitude greater than or equal to ½ a quantization step width of the quantizer.

7. The ΔΣ modulator as claimed in claim 4 , wherein
the quantization step width is set to be greater than or equal to two times and less than or equal to eight times a root-mean-square value of an input-referred noise of the quantizer.

8. The ΔΣ modulator as claimed in claim 5 , wherein
the quantization step width is set to be greater than or equal to two times and less than or equal to eight times a root-mean-square value of an input-referred noise of the quantizer.

9. The ΔΣ modulator as claimed in claim 6 , wherein
the quantization step width is set to be greater than or equal to two times and less than or equal to eight times a root-mean-square value of an input-referred noise of the quantizer.

10. The ΔΣ modulator as claimed in claim 1 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

11. The ΔΣ modulator as claimed in claim 2 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

12. The ΔΣ modulator as claimed in claim 3 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

13. The ΔΣ modulator as claimed in claim 4 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

14. The ΔΣ modulator as claimed in claim 5 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

15. The ΔΣ modulator as claimed in claim 6 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

16. The ΔΣ modulator as claimed in claim 7 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

17. The ΔΣ modulator as claimed in claim 8 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

18. The ΔΣ modulator as claimed in claim 9 , wherein
the quantizer, the digital integrator and the D/A converter operate in synchronization with each other by the same clock signal.

19. The ΔΣ modulator as claimed in claim 1 , wherein
the digital integrator is such that two or more of the digital integrators are connected in a cascade manner.

20. The ΔΣ modulator as claimed in claim 2 , wherein
the digital integrator is such that two or more of the digital integrators are connected in a cascade manner.

Assignees

• Toyota Motor Co Ltd

Inventors

• Watanabe Hikaru

Classifications

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/364 Primary

  by resetting one or more loop filter stages · CPC title

• H03M3/472

  Shared, i.e. using a single converter for multiple channels · CPC title

• H03M3/328

  using dither · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title