Electric circuit

Patent metadata

Field	Value
Publication number	US-9419570-B2
Application number	US-201414475611-A
Country	US
Kind code	B2
Filing date	Sep 3, 2014
Priority date	Nov 28, 2001
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A transistor has variation in a threshold voltage or mobility due to accumulation of factors such as variation in a gate insulating film which is caused by a difference of a manufacturing process or a substrate to be used and variation in a crystal state of a channel formation region. The present invention provides an electric circuit which is arranged such that both electrodes of a capacitance device can hold a voltage between the gate and the source of a specific transistor. Further, the present invention provides an electric circuit which has a function capable of setting a potential difference between both electrodes of a capacitance device so as to be a threshold voltage of a specific transistor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first line, a second line, a third line, and a fourth line;
a first transistor, a second transistor, and a third transistor each including a gate, a source and a drain;
a first capacitor configured to store voltage depending on threshold voltage of the second transistor; and
an element including an anode and a cathode,
wherein the gate of the first transistor is electrically connected to the first line,
wherein one of the source and the drain of the first transistor is electrically connected to the second line,
wherein the other of the source and the drain of the first transistor is electrically connected to the second transistor,
wherein the gate of the second transistor is electrically connected to one terminal of the first capacitor,
wherein one of the source and the drain of the second transistor is electrically connected to the third line,
wherein the other of the source and the drain of the second transistor is electrically connected to the other terminal of the first capacitor;
wherein the gate of the third transistor is electrically connected to the fourth line,
wherein one of the source and the drain of the third transistor is electrically connected to one of the anode and the cathode,
wherein the one of the anode and the cathode is electrically connected to the other terminal of the first capacitor,
wherein a first potential is capable of being supplied to the second line,
wherein a second potential is capable of being supplied to the third line, and
wherein the first potential is different form the second potential.

2. The semiconductor device according to claim 1 , further comprising:
a bias circuit electrically connected to the second line.

3. The semiconductor device according to claim 2 ,
wherein the bias circuit comprises:
a fourth transistor including a gate, a source, and a drain;
a second capacitor including a first terminal and a second terminal; and
a first switch, a second switch, and a third switch each including a first terminal and a second terminal,

wherein one of the source and the drain of the fourth transistor and the first terminal of the first switch are electrically connected to the second line,
wherein the gate of the fourth transistor is electrically connected to the second terminal of the first switch and the first terminal of the second capacitor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the first terminal of the second switch, and
wherein the second terminal of the second capacitor is electrically connected to the second terminal of the second switch and the first terminal of the third switch.

4. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the third transistor is electrically connected to the third line.

5. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor.

6. The semiconductor device according to claim 1 , wherein the cathode is electrically connected to the other terminal of the first capacitor.

7. The semiconductor device according to claim 1 , wherein the element is a photoelectric converter device.

8. The semiconductor device according to claim 1 , further comprising:
a fifth line; and
a fourth transistor including a gate, a source, and a drain,
wherein the gate of the fourth transistor is electrically connected to the fifth line, and
wherein the other of the source and the drain of the second transistor is electrically connected to the other terminal of the first capacitor through the fourth transistor.

9. The semiconductor device according to claim 1 , further comprising:
a fifth line; and
a fourth transistor including a gate, a source, and a drain,
wherein the gate of the fourth transistor is electrically connected to the fifth line,
wherein one of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor, and
wherein the other of the source and the drain of the fourth transistor is electrically connected to the one of the source and the drain of the second transistor.

10. The semiconductor device according to claim 1 , further comprising:
a fifth line; and
a fourth transistor including a gate, a source, and a drain,
wherein the gate of the fourth transistor is electrically connected to the fifth line,
wherein the element is electrically connected to the other terminal of the first capacitor through the fourth transistor.

11. An electric apparatus comprising:
the semiconductor device according to claim 1 ; and
at least one of a display part, an image receiving part, an operation keys, and a speaker part.

12. A semiconductor device comprising:
a first line, a second line, and a third line;
a first transistor, a second transistor, and a third transistor each including a gate, a source and a drain;
a first capacitor configured to store voltage depending on threshold voltage of the second transistor; and
an element including an anode and a cathode,
wherein the gate of the first transistor is electrically connected to the first line,
wherein one of the source and the drain of the first transistor is electrically connected to the second line,
wherein the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one terminal of the first capacitor
wherein one of the source and the drain of the second transistor is electrically connected to the other terminal of the first capacitor,
wherein the one of the source and the drain of the second transistor is electrically connected to one of the anode and the cathode,
wherein the gate of the third transistor is electrically connected to the third line,
wherein one of the source and the drain of the third transistor is electrically connected to the element,
wherein a first potential is capable of being supplied to the first line,
wherein a second potential is capable of being supplied to the third line, and
wherein the first potential is different form the second potential.

13. The semiconductor device according to claim 12 , further comprising:
a fourth transistor;
a fourth line electrically connected to the one of the source and the drain of the second transistor through the fourth; and
a bias circuit electrically connected to the second line.

14. The semiconductor device according to claim 13 ,
wherein the bias circuit comprises:
a fifth transistor including a gate, a source, and a drain;
a second capacitor including a first terminal and a second terminal; and
a first switch, a second switch, and a third switch each including a first terminal and a second terminal,

wherein one of the source and the drain of the fifth transistor and the first terminal of the first switch are electrically connected to the fourth line,
wherein the gate of the fifth transistor is electrically connected to the second terminal of the first switch and the first terminal of the second capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first terminal of the second switch, and
wherein the second terminal of the second capacitor is electrically connected to the second terminal of the second switch and the first terminal of the third switch.

15. The se

Assignees

• Semiconductor Energy Lab

Inventors

• Kimura Hajime
• Watanabe Yasuko

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H03F3/45076

  characterised by the way of implementation of the active amplifying circuit in the differential amplifier · CPC title

• H03F2203/45628

  the LC comprising bias stabilisation means, e.g. DC level stabilisation means, and temperature coefficient dependent control, e.g. DC level shifting means · CPC title

• H03K19/01728

  in synchronous circuits, i.e. by using clock signals · CPC title

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title