Amplifiers and related integrated circuits

Patent metadata

Field	Value
Publication number	US-9419566-B2
Application number	US-201114009099-A
Country	US
Kind code	B2
Filing date	Apr 20, 2011
Priority date	Apr 20, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Apparatus are provided for amplifier systems and related integrated circuits are provided. An exemplary integrated circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first output of the integrated circuit, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the integrated circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.

First claim

What is claimed is:

1. A circuit comprising:
a first amplifier arrangement having a first amplifier output;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology;
a second amplifier arrangement having a second amplifier output; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein the first impedance matching circuitry causes a phase of the signal at the first output of the integrated circuit to be shifted by 90 degrees relative to the signal at the first amplifier output, and the second impedance matching circuitry causes a phase of the signal at the second output of the integrated circuit to be shifted by 180 degrees relative to the signal at the second amplifier output.

2. A circuit comprising:
a first amplifier arrangement having a first amplifier output, wherein the first amplifier arrangement is configured to operate in Class AB mode;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology;
a second amplifier arrangement having a second amplifier output, wherein the second amplifier arrangement is configured to operate in Class C mode; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein a phase inversion provided by the first impedance matching circuitry and a phase inversion provided by the second impedance matching circuitry are different.

3. The circuit of claim 2 , wherein the first impedance matching circuitry provides a single phase inversion and the second impedance matching circuitry provides a double phase inversion.

4. The circuit of claim 2 , wherein a physical topology of the second impedance matching circuitry and a physical topology of the first impedance matching circuitry are different.

5. A circuit comprising:
a first amplifier arrangement having a first amplifier output;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology, wherein the first impedance matching circuitry causes a phase of the si nal at an output of the first impedance matching circuitry to be shifted by 90 degrees relative to the signal at the output of the first amplifier arrangement, and wherein the first impedance matching circuitry comprises:
a first inductive element coupled between a first node and the first output, the first node being coupled to the first amplifier output,
a second inductive element coupled to the first node, and
a first capacitive element coupled between the second inductive element and a ground reference voltage node, such that the second inductive element and the first capacitive element are configured electrically in series between the first node and the ground reference voltage node;

a second amplifier arrangement having a second amplifier output; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein the second impedance matching circuitry causes a phase of the signal at an output of the second impedance matching circuitry to be shifted by 180 degrees relative to the signal at the output of the second amplifier arrangement, wherein the second impedance matching circuitry comprises:
a third inductive element coupled between the second amplifier output and a second node,
a fourth inductive element coupled between the second node and the second output, and
a second capacitive element coupled between the second node and the ground reference voltage node.

6. A circuit comprising:
a first amplifier arrangement having a first amplifier output, wherein the first amplifier arrangement comprises a first transistor configured to operate in Class AB mode;
first impedance matching circuitry coupled between the first amplifier output and a first output of the circuit, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology, wherein the first impedance matching circuitry comprises:
a first inductive element coupled between a first node and the first output, the first node being coupled to the first amplifier output,
a second inductive element coupled to the first node, and
a first capacitive element coupled between the second inductive element and a ground reference voltage node, such that the second inductive element and the first capacitive element are configured electrically in series between the first node and the ground reference voltage node;

a second amplifier arrangement having a second amplifier output, wherein the second amplifier arrangement comprises a second transistor configured to operate in Class C mode; and
second impedance matching circuitry coupled between the second amplifier output and a second output of the circuit, wherein a topology of the second impedance matching circuitry and a topology of the first impedance matching circuitry are different, and wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology, and wherein a phase inversion provided by the first impedance matching circuitry and a phase inversion provided by the second impedance matching circuitry are different, wherein the second impedance matching circuitry comprises:
a third inductive element coupled between the second amplifier output and a second node,
a fourth inductive element coupled between the second node and the second output, and
a second capacitive element coupled between the second node and the around reference voltage node.

7. The circuit of claim 6 , wherein:
the first inductive element comprises a first wire connected between the first amplifier arrangement and the first output;
the second inductive element comprises a second wire connected between the first amplifier arrangement and the first capacitive element;
the third inductive element comprises a third wire connected between the second amplifier arrangement and the second capacitive element; and
the fourth inductive element comprises a fourth wire connected between the second capacitive element and the second output.

8. The circuit of claim 7 , further comprising a metal substrate configured to provide the ground reference voltage node, wherein:
the first capacitive element and the second capacitive element are each disposed on the metal substrate;
the first amplifier arrangement comprises a first transistor disposed on the metal substrate, the first transistor including a first contact region for the first amplifier output;
the first wire is connected between the first contact region and the first output;
the second wire is con

Assignees

• Noori Basim H
• Bouisse Gerard J
• Jones Jeffrey K
• Nanan Jean-Christophe
• Pla Jaime A
• Freescale Semiconductor Inc

Inventors

• Noori Basim H
• Bouisse Gerard J
• Jones Jeffrey K
• Nanan Jean-Christophe
• Pla Jaime A

Classifications

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H03F1/0288 Primary

  using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers · CPC title