Passivation and alignment of piezoelectronic transistor piezoresistor

Patent metadata

Field	Value
Publication number	US-9419203-B2
Application number	US-201514747223-A
Country	US
Kind code	B2
Filing date	Jun 23, 2015
Priority date	Oct 31, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.

First claim

What is claimed is:

1. A piezoelectronic transistor (PET) device, comprising:
a first metal layer;
a layer of piezoelectric (PE) element formed on the first metal layer;
a second metal layer on the PE element;
piezoresistive (PR) material formed in a well above the second metal layer and above the well, sides of the well being lined with a passivation film and a diameter of the PR material formed above the well being greater than a diameter of the well;
a passivation layer and a top metal layer formed above the PR material at the diameter of the PR material above the well, a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer being a T-shaped structure; and
a metal clamp layer as a top layer of the PET device.

2. The PET device according to claim 1 , further comprising a spring on the second metal layer adjacent to the T-shaped structure.

3. The PET device according to claim 2 , wherein the spring is electrically connected to the metal clamp layer through vias.

4. The PET device according to claim 2 , wherein the spring is comprised of ruthenium (Ru) and titanium nitride (TiN).

5. The PET device according to claim 1 , wherein the metal clamp layer is aligned with the T-shaped structure to ensure a close contact between the PR material in the well and the second metal layer above the PE element.

6. The PET device according to claim 1 , wherein an edge of the T-shaped structure above the well is lined with the passivation film.

7. A semiconductor device, comprising:
a piezoelectronic transistor (PET) device comprising
a first metal layer;
a layer of piezoelectric (PE) element formed on the first metal layer;
a second metal layer on the PE element;
piezoresistive (PR) material formed in a well above the second metal layer and above the well, sides of the well being lined with a passivation film and a diameter of the PR material formed above the well being greater than a diameter of the well;
a passivation layer and a top metal layer formed above the PR material at the diameter of the PR material above the well, a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer being a T-shaped structure; and
a metal clamp layer as a top layer of the PET device; and

a voltage source configured to apply a voltage between the first metal layer and the second metal layer.

8. The semiconductor device according to claim 7 , further comprising a spring on the second metal layer adjacent to the T-shaped structure.

9. The semiconductor device according to claim 8 , wherein the spring is electrically connected to the metal clamp layer through vias.

10. The semiconductor device according to claim 8 , wherein the spring is comprised of ruthenium (Ru) and titanium nitride (TiN).

11. The semiconductor device according to claim 7 , wherein the metal clamp layer is aligned with the T-shaped structure to ensure a close contact between the PR material in the well and the second metal layer above the PE element.

12. The semiconductor device according to claim 7 , wherein an edge of the T-shaped structure above the well is lined with the passivation film.

Assignees

• IBM

Inventors

• Bryce Brian A
• Chang Josephine B
• Copel Matthew W
• Kuroda Marcelo A

Classifications

• H01L41/083 Primary

  Electricity · mapped topic

• H01L41/0477

  Electricity · mapped topic

• H10N99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10N30/074

  by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing · CPC title

• H10N30/082

  by etching, e.g. lithography · CPC title