US9419201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9419201-B2 |
| Application number | US-201514747194-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 23, 2015 |
| Priority date | Oct 31, 2014 |
| Publication date | Aug 16, 2016 |
| Grant date | Aug 16, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.
Opening claim text (preview).
What is claimed is: 1. A piezoelectronic transistor (PET) device, comprising: a first stack including dielectric layers; a first metal layer formed over the first stack; a piezoelectric (PE) material formed over the first metal layer; a second metal layer on the PE material; and a layer comprising a piezoresistive (PR) element and a passivation layer disposed on the second metal layer, the passivation layer filling a gap in a membrane to hermetically seal the PET device. 2. The PET device according to claim 1 , wherein the first metal layer, the PE material, and the second metal layer are arranged in a plurality of second stacks over the first stack, each of the plurality of second stacks including the first metal layer, the PE material, and the second metal layer. 3. The PET device according to claim 2 , further comprising a bridge formed of titanium (Ti) between the second metal layer of two of the plurality of second stacks. 4. The PET device according to claim 1 , further comprising an aluminum clamp layer formed on the passivation layer. 5. A semiconductor device, comprising: a piezoelectronic transistor (PET) device comprising a first stack including dielectric layers, a first metal layer formed over the first stack, a piezoelectric (PE) material formed over the first metal layer, a second metal layer on the PE material, and a layer comprising a piezoresistive (PR) element and a passivation layer disposed on the second metal layer, the passivation layer filling a gap in a membrane to hermetically seal the PET device; and a voltage source configured to apply a voltage between the first metal layer and the second metal layer. 6. The semiconductor device according to claim 5 , wherein the first metal layer, the PE material, and the second metal layer are arranged in a plurality of second stacks over the first stack, each of the plurality of second stacks including the first metal layer, the PE material, and the second metal layer. 7. The semiconductor device according to claim 6 , further comprising a bridge formed of titanium (Ti) between the second metal layer of two of the plurality of second stacks. 8. The semiconductor device according to claim 5 , further comprising an aluminum clamp layer formed on the passivation layer.
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Subject matter not provided for in other groups of this subclass · CPC title
by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.