Bidirectional trench FET with gate-based resurf

Patent metadata

Field	Value
Publication number	US-9419128-B2
Application number	US-201514926288-A
Country	US
Kind code	B2
Filing date	Oct 29, 2015
Priority date	Aug 12, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

First claim

The invention claimed is:

1. A device comprising:
a semiconductor substrate having a surface;
a trench in the semiconductor substrate extending vertically from the surface;
a body region disposed in the semiconductor substrate laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation;
a drift region disposed in the semiconductor substrate between the body region and the surface, and having a second conductivity type;
a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage to control formation of the channel during operation; and
a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region;
wherein the gate structure and the gate dielectric layer vertically overlap the drift region to establish a gate-drift overlap greater than an extent to which the gate structure extends beyond a bottom of the body region.

2. The device of claim 1 , wherein:
the gate structure has a boundary disposed at a depth between the surface and the body region; and
the depth of the boundary is positioned about halfway between the surface and the body region.

3. The device of claim 1 , wherein:
the gate structure has a boundary disposed at a depth between the surface and the body region; and
the depth of the boundary is positioned at about a midpoint of the drift region.

4. The device of claim 1 , wherein a vertical extent of the gate structure and the gate dielectric layer is greater than or about equal to twice a vertical extent of the body region.

5. The device of claim 1 , wherein the gate-drift overlap is greater than or about equal to a width of the body region.

6. The device of claim 1 , wherein the gate-drift overlap is greater than a fabrication tolerance directed to ensure formation of the channel across the body region.

7. The device of claim 1 , further comprising:
a further drift region disposed between the body region and a backside surface of the semiconductor substrate and having the second conductivity type; and
a shield structure disposed in the trench adjacent the further drift region and spaced from the gate structure, wherein:
the trench comprises a further dielectric layer between the shield structure and the further drift region; and
the further dielectric layer is thicker than the gate dielectric layer.

8. The device of claim 7 , wherein the first-named and further drift regions have different dopant concentration levels.

9. The device of claim 7 , wherein the trench is shield-free along the first-named drift region.

10. A bidirectional trench field effect transistor (FET) device comprising:
a semiconductor substrate having a topside surface and a backside surface opposite from the topside surface; and
a plurality of transistor structures disposed in the semiconductor substrate, each transistor structure comprising:
a trench extending vertically from the topside surface;
a body region adjacent the trench, having a first conductivity type, and in which a channel is formed during operation;
an upper drift region disposed between the body region and the topside surface and having a second conductivity type;
a lower drift region disposed between the body region and the backside surface and having the second conductivity type;
a gate structure disposed in the trench alongside the body region, and configured to receive a control voltage to control formation of the channel during operation;
a shield disposed in the trench and spaced from the gate structure;
a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region; and
a further dielectric layer disposed along the sidewall between the shield and the lower drift region, the further dielectric layer being thicker than the gate dielectric layer;

wherein the gate structure has a boundary disposed at a depth between the topside surface and the body region, the depth being spaced from the body region such that the gate structure and the gate dielectric layer are disposed alongside the upper drift region to establish a gate-drift overlap greater than an extent to which the gate structure extends beyond a bottom of the body region.

11. The bidirectional trench FET device of claim 10 , wherein the depth of the boundary is positioned about halfway between the topside surface and the body region.

12. The bidirectional trench FET device of claim 10 , wherein the depth of the boundary is positioned such that the gate structure extends beyond the body region alongside the upper drift region to an extent greater than or about equal to a thickness of the further dielectric layer.

13. The bidirectional trench FET device of claim 10 , wherein the depth of the boundary is positioned such that the gate structure extends beyond the body region to an extent greater than or about equal to a lateral width of the shield.

14. The bidirectional trench FET device of claim 10 , wherein the trench does not include an upper shield disposed along the upper drift region.

15. A method of fabricating a device in a semiconductor substrate, the method comprising:
implanting dopant of a first conductivity type to form a body region buried in the semiconductor substrate, the body region defining a boundary with a drift region disposed between the body region and a surface of the semiconductor substrate;
forming a trench in the semiconductor substrate that extends vertically from the surface of the semiconductor substrate, the trench being disposed laterally adjacent to the body region and the drift region;
forming a gate dielectric layer in the trench along a sidewall of the trench; and
forming a gate structure in the trench adjacent the gate dielectric layer and alongside the body region;
wherein forming the gate structure comprises etching a gate conductive layer to recess the gate structure from the surface of the semiconductor substrate to an extent that the gate structure and the gate dielectric layer vertically overlap the drift region to establish a gate-drift overlap greater than an extent to which the gate structure extends beyond a bottom of the body region.

16. The method of claim 15 , wherein:
the gate structure has a boundary disposed at a depth between the surface and the body region; and
the depth of the boundary is positioned about halfway between the surface and the body region.

17. The method of claim 15 , further comprising, before forming the gate dielectric layer:
depositing a further dielectric layer along the sidewall of the trench, the further dielectric layer being thicker than the gate dielectric layer;
forming a shield in the trench adjacent to the further dielectric layer.

18. The method of claim 15 , further comprising growing an epitaxial layer to define the surface of the semiconductor substrate and establish a dopant concentration level of the drift region.

19. The method of claim 18 , wherein the dopant concentration level of the drift region is different than a dopant concentration level of a region of the semiconductor substrate below the body region through which charge carriers drift during operation.

20. The method of claim 15 , further comprising doping the drift region to establish a different dopant concentration level for the drift region relative to a region of the semiconductor substrate below the body region through which charge carriers drift during operation

Assignees

• Zitouni Moaniss
• De Frésart Edouard D
• Ku Pon Sung
• Petras Michael F
• Qin Ganming
• Stefanov Evgueniy N
• Zupac Dragan
• Freescale Semiconductor Inc

Inventors

• Zitouni Moaniss
• De Frésart Edouard D
• Ku Pon Sung
• Petras Michael F
• Qin Ganming
• Stefanov Evgueniy N
• Zupac Dragan

Classifications

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title