Semiconductor device, and manufacturing method for same

Patent metadata

Field	Value
Publication number	US-9419117-B2
Application number	US-201214236567-A
Country	US
Kind code	B2
Filing date	Jul 30, 2012
Priority date	Aug 2, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

The present invention is directed to a semiconductor device including a semiconductor chip formed with an SiC-IGBT including an SiC semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the SiC semiconductor layer, a second conductive-type base region formed such that the base region is in contact with the collector region, a first conductive-type channel region formed such that the channel region is in contact with the base region, a second conductive-type emitter region formed such that the emitter region is in contact with the channel region to define a portion of a first surface of the SiC semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region, and a MOSFET including a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode, the MOSFET connected in parallel to the SiC-IGBT.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including:
an SiC semiconductor layer having a first surface and a second surface,
a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,
a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,
a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,
a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,
a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and
an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and
a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including:
a second conductive-type source region electrically connected to the emitter electrode; and
a second conductive-type drain region electrically connected to the collector electrode, wherein
the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,
the source region is formed utilizing the emitter region of the SiC-IGBT,
the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,
the collector electrode is collectively connected to the drain region and the collector region,
the SiC semiconductor layer includes:
a second conductive-type SiC substrate defining the second surface of the SiC semiconductor layer and selectively formed with a trench from the second surface toward the first surface, and
a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein
the drain region is formed utilizing the SiC substrate, and
the collector region is formed at the bottom surface of the trench.

2. The semiconductor device according to claim 1 , wherein a plurality of the trenches are formed in a striped manner.

3. The semiconductor device according to claim 1 , wherein a deepest portion of the trench reaches the interface between the SiC substrate and the SiC base layer.

4. A semiconductor device comprising:
a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including:
an SiC semiconductor layer having a first surface and a second surface,
a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,
a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,
a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,
a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,
a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and
an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and
a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including:
a second conductive-type source region electrically connected to the emitter electrode; and
a second conductive-type drain region electrically connected to the collector electrode, wherein
the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,
the source region is formed utilizing the emitter region of the SiC-IGBT,
the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,
the collector electrode is collectively connected to the drain region and the collector region,
the SiC semiconductor layer includes:
a first conductive-type SiC substrate defining the second surface of the SiC semiconductor layer and selectively formed with a trench from the second surface toward the first surface, and
a second conductive-type SiC base layer formed on the SiC substrate to serve as the base region defining the first surface of the SiC semiconductor layer, wherein
the collector region is formed utilizing the SiC substrate, and
the drain region is formed at the bottom surface of the trench.

5. A semiconductor device comprising:
a semiconductor chip formed with an SiC-IGBT (Insulated Gate Bipolar Semiconductor) including:
an SiC semiconductor layer having a first surface and a second surface,
a first conductive-type collector region formed such that the collector region is exposed on the second surface of the SiC semiconductor layer,
a second conductive-type base region formed closer to the first surface of the SiC semiconductor layer with respect to the collector region such that the base region is in contact with the collector region,
a first conductive-type channel region formed closer to the first surface of the SiC semiconductor layer with respect to the base region such that the channel region is in contact with the base region,
a second conductive-type emitter region formed closer to the first surface of the SiC semiconductor layer with respect to the channel region such that the emitter region is in contact with the channel region, the emitter region defining a portion of the first surface of the SiC semiconductor layer,
a collector electrode formed such that the collector electrode is in contact with the second surface of the SiC semiconductor layer, the collector electrode connected to the collector region, and
an emitter electrode formed such that the emitter electrode is in contact with the first surface of the SiC semiconductor layer, the emitter electrode connected to the emitter region; and
a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected in parallel to the SiC-IGBT, the MOSFET including:
a second conductive-type source region electrically connected to the emitter electrode; and
a second conductive-type drain region electrically connected to the collector electrode, wherein
the MOSFET includes an SiC-MOSFET provided in the semiconductor chip,
the source region is formed utilizing the emitter region of the SiC-IGBT,
the drain region is formed adjacent to the collector region of the SiC-IGBT such that the drain region is selectively exposed on the second surface of the SiC semiconductor layer,
the collector electrode is

Assignees

• Aketa Masatoshi
• Nakano Yuki
• Rohm Co Ltd

Inventors

• Aketa Masatoshi
• Nakano Yuki

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/07554

  changes in dispositions · CPC title