Array substrate, method for fabricating the same and display device

Patent metadata

Field	Value
Publication number	US-9419027-B2
Application number	US-201514802241-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	May 30, 2013
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate comprises a plurality of gate lines and a plurality of data lines which intersect each other to define a plurality of pixel regions, each of the pixel regions comprises a thin film transistor and further comprises: a base substrate; more than one protrusion disposed apart from each other on the base substrate; a first electrode layer comprising at least one first electrode strip disposed in a gap between adjacent protrusions; a second electrode layer comprising at least one second electrode strip disposed on the protrusions.

First claim

What is claimed is:

1. A method for fabricating an array substrate, comprising forming gate lines, data lines and a TFT on a base substrate, the method further comprises:
forming more than one protrusion disposed apart from each other on the base substrate;
forming a first electrode layer, the first electrode layer comprises at least one first electrode strip disposed in a gap between adjacent protrusions;
forming a second electrode layer, the second electrode layer comprises at least one second electrode strip disposed on the protrusions.

2. The method of claim 1 , further comprising fabricating an insulation layer between the first electrode layer and the second electrode layer.

3. The method of claim 2 , comprising:
fabricating more than one protrusion disposed apart from each other on the base substrate;
fabricating a first transparent conductive film on the substrate having the protrusions formed thereon and coating a first photoresist on the substrate having the first transparent conductive film fabricated thereon;
performing an ashing process on the first photoresist to form a pattern of the first photoresist which only covers gaps between the protrusions;
performing an etching process to remove the first transparent conductive film not covered by the pattern of the first photoresist;
performing a photoresist peeling process on the pattern of the first photoresist to form the first electrode layer comprising at least one first electrode strip;
fabricating an insulation layer on the base substrate having the first electrode layer formed thereon;
coating a second photoresist on the substrate having the insulation layer fabricated thereon, and performing an ashing process on the second photoresist to form a pattern of the second photoresist which only covers gaps between the protrusions;
fabricating a second transparent conductive film on the substrate having the pattern of the second photoresist formed thereon, and then removing the pattern of the second photoresist and the second transparent conductive film on the pattern of the second photoresist through a photoresist peeling process to form the second electrode layer comprising at least one second electrode strip.

4. The method of claim 1 , wherein the protrusions fabricated on the base substrate are equally spaced apart from each other.

5. The method of claim 1 , wherein a material of the protrusion is transparent resin material, and a thickness of the protrusion is larger than that of the first electrode.

6. The method of claim 2 , wherein the TFT comprises a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode;
the insulation comprises at least one of the gate insulation layer or a passivation layer;
the first electrode layer is connected to the drain electrode, or the second electrode layer is connected to the drain electrode.

7. The method of claim 2 , wherein the protrusions fabricated on the base substrate are equally spaced apart from each other.

8. The method of claim 2 , wherein a material of the protrusion is transparent resin material, and a thickness of the protrusion is larger than that of the first electrode.

9. The method of claim 3 , wherein the TFT comprises a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode;
the insulation comprises at least one of the gate insulation layer or a passivation layer;
the first electrode layer is connected to the drain electrode, or the second electrode layer is connected to the drain electrode.

10. The method of claim 3 , wherein the protrusions fabricated on the base substrate are equally spaced apart from each other.

11. The method of claim 3 , wherein a material of the protrusion is transparent resin material, and a thickness of the protrusion is larger than that of the first electrode.

12. The method of claim 4 , wherein a material of the protrusion is transparent resin material, and a thickness of the protrusion is larger than that of the first electrode.

13. The method of claim 6 , wherein the protrusions fabricated on the base substrate are equally spaced apart from each other.

14. The method of claim 6 , wherein a material of the protrusion is transparent resin material, and a thickness of the protrusion is larger than that of the first electrode.

Assignees

• Boe Technology Group Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Choi Seungjin
• Kim Heecheol
• Song Youngsuk
• Yoo Seongyeol

Classifications

• H10P50/286

  of organic materials · CPC title

• H10P50/264

  by chemical means · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title