High aspect ratio etching method

Patent metadata

Field	Value
Publication number	US-9419010-B2
Application number	US-201414488937-A
Country	US
Kind code	B2
Filing date	Sep 17, 2014
Priority date	Feb 24, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer is formed on side surfaces of active strips in the first plurality of trenches, and a first layer of conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of active strips between a second plurality of trenches of the plurality of semiconductor layers. A second memory layer is formed on side surfaces of active strips in the second plurality of trenches, and a second layer of conductive material is formed over the second memory layer. Channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.

First claim

What is claimed is:

1. A method for manufacturing a memory device, comprising:
forming a plurality of semiconductor layers alternating with insulating layers on an integrated circuit substrate;
etching the plurality of semiconductor layers to define a first plurality of stacks of active strips between a first plurality of trenches; and
etching the first plurality of stacks to divide each stack in the first plurality of stacks into two stacks in a second plurality of stacks of active strips of the plurality of semiconductor layers, wherein each stack in the second plurality of stacks is defined between a first trench in the first plurality of trenches and a second trench in a second plurality of trenches;
wherein channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.

2. The method of claim 1 , further comprising:
after the first plurality of stacks is defined and before the second plurality of stacks is defined,
forming a first memory layer on side surfaces of active strips in the first plurality of stacks in the first plurality of trenches; and
forming a first layer of conductive material over and having a surface conformal with the first memory layer.

3. The method of claim 1 , further comprising:
forming a second memory layer on side surfaces of active strips in the second plurality of stacks in the second plurality of trenches; and
forming a second layer of conductive material over and having a surface conformal with the second memory layer.

4. The method of claim 1 , comprising:
forming horizontal conductive lines connecting a first plurality of conductive lines in the first plurality of trenches and a second plurality of conductive lines in the second plurality of trenches to a row decoder in the memory device.

5. The method of claim 1 , comprising:
forming bit line structures connecting active strips in the second plurality of stacks of active strips to a column decoder in the memory device.

6. The method of claim 1 , comprising:
etching the second plurality of stacks to divide each stack in the second plurality of stacks into two stacks in a third plurality of stacks of active strips of the plurality of semiconductor layers, wherein the stack in the first plurality of stacks has a width substantially equal to seven times a width of a stack in the third plurality of stacks.

7. A method for manufacturing a memory device, comprising:
forming a plurality of semiconductor layers alternating with insulating layers on an integrated circuit substrate;
etching the plurality of semiconductor layers to define a first plurality of stacks of active strips between a first plurality of trenches;
etching the first plurality of stacks to divide each stack in the first plurality of stacks into two stacks in a second plurality of stacks of active strips of the plurality of semiconductor layers, wherein each stack in the second plurality of stacks is defined between a first trench in the first plurality of trenches and a second trench in a second plurality of trenches;
before the second plurality of stacks is defined, forming a first memory layer on side surfaces of active strips in the first plurality of stacks in the first plurality of trenches, and forming a first layer of conductive material over and having a surface conformal with the first memory layer; and
forming a second memory layer on side surfaces of active strips in the second plurality of stacks in the second plurality of trenches, and forming a second layer of conductive material over and having a surface conformal with the second memory layer.

8. The method of claim 7 , further comprising:
after a second memory layer is formed on side surfaces of active strips in the second plurality of stacks in the second plurality of trenches, and a second layer of conductive material is formed over and having a surface conformal with the second memory layer,
etching the first layer of conductive material to define a first plurality of conductive lines in the first plurality of trenches, arranged orthogonally over the active strips in the first plurality of stacks, and having surfaces conformal with the first memory layer, defining memory cells in interface regions at cross-points between side surfaces of the active strips in the first plurality of stacks and the first plurality of conductive lines in the first plurality of trenches.

9. The method of claim 8 , comprising:
etching the first memory layer to define a first memory formation in the first plurality of trenches, arranged orthogonally over the active strips in the first plurality of stacks, and having surfaces conformal with conductive lines in the first plurality of conductive lines.

10. The method of claim 8 , comprising:
removing excess conductive material in the first layer of conductive material and excess memory material in the first memory layer outside the interface regions and in the first plurality of trenches.

11. The method of claim 7 , further comprising:
after a plurality of conductive lines is defined in the first plurality of trenches, etching the second layer of conductive material to define a second plurality of conductive lines in the second plurality of trenches, arranged orthogonally over, and having surfaces conformal with, the second memory layer, defining memory cells in interface regions at cross-points between side surfaces of the active strips in the second plurality of stacks and the second plurality of conductive lines in the second plurality of trenches.

12. The method of claim 11 , comprising:
etching the second memory layer to define a second memory formation in the second plurality of trenches, arranged orthogonally over the active strips in the second plurality of stacks, and having surfaces conformal with conductive lines in the second plurality of conductive lines.

13. The method of claim 11 , comprising:
removing excess conductive material in the second layer of conductive material and excess memory material in the second memory layer outside the interface regions and in the second plurality of trenches.

14. The method of claim 7 , further comprising:
after the first layer of conductive material is formed, and
after a second memory layer is formed on side surfaces of active strips in the second plurality of stacks in the second plurality of trenches, and a second layer of conductive material is formed over and having a surface conformal with the second memory layer,
etching the first layer and the second layer of conductive material, using a single hard mask, to define a plurality of conductive lines in the first plurality of trenches and the second plurality of trenches, arranged orthogonally over, and having surfaces conformal with, the first memory layer and the second memory layer, defining memory cells in interface regions at cross-points between side surfaces of the active strips in the first plurality and second plurality of stacks and the plurality of conductive lines.

15. The method of claim 14 , comprising:
etching the first memory layer and the second memory layer to define a memory formation in the first plurality of trenches and the second plurality of trenches, arranged orthogonally over the active strips in the first plurality of stacks and the second plurality of stacks, and having surfaces conformal with conductive lines in the plurality of conductive lines.

16. The method of claim 14 , comprising:
removing excess conductive material in the first layer of conductive material and excess memory material in

Assignees

• Macronix Int Co Ltd

Inventors

• Shih Yen-Hao
• Chen Chih-Ping
• Lai Sheng-Chih

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic