Semiconductor device, related manufacturing method, and related electronic device

Patent metadata

Field	Value
Publication number	US-9419005-B2
Application number	US-201414578937-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	May 23, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A method for manufacturing a semiconductor device may include the following steps: preparing a stacked structure; processing the stacked structure to form a first gate structure and a preliminary structure; forming a dielectric material layer that covers at least the first gate structure; forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure; performing an annealing process on at least one of the dielectric material layer and the dielectric layer; processing the preliminary structure to form a second gate structure; and after the annealing process has been performed, forming a first metal silicide member on the second gate structure and/or forming a second metal silicide member on an active region associated with the second gate structure.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
preparing a stacked structure;
processing the stacked structure to form a first gate structure and a preliminary structure;
forming a dielectric material layer that covers at least the first gate structure;
forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure;
performing an annealing process on at least one of the dielectric material layer and the dielectric layer to optimize a property of the dielectric layer;
after the annealing process has been performed, processing the preliminary structure to form a second gate structure; and
after the second gate structure has been formed, performing no annealing process that can change the property of the dielectric layer on any elements of the semiconductor device, and performing at least one of forming a first metal silicide member on the second gate structure and forming a second metal silicide member on an active region associated with the second gate structure.

2. The method of claim 1 , wherein the stacked structure includes a semiconductor substrate, a floating-gate material layer, a control-gate material layer, and a mask material layer, wherein the floating-gate material layer is positioned between the semiconductor substrate and the control-gate material layer, and wherein the control-gate material layer is positioned between the floating-gate material layer and the mask material layer.

3. The method of claim 1 , wherein the first gate structure is positioned in a cell region of the semiconductor device, and wherein the second gate structure is positioned in a peripheral region of the semiconductor device.

4. The method of claim 1 , further comprising: forming two sidewall layers on two opposite sides of the first gate structure, such that the first gate structure is positioned between the two sidewall layers, wherein the dielectric material layer is subsequently formed and covers the sidewall layers.

5. The method of claim 4 , further comprising: after the sidewall layers have been formed, forming two lightly-doped drain regions at the two opposite sides of the first gate structure.

6. The method of claim 4 , further comprising: after the sidewall layers have been formed, forming a source region and a drain region at the two opposite sides of the first gate structure.

7. The method of claim 1 , further comprising: forming two sidewall layers on two opposite sides of the second gate structure after the annealing process has been performed.

8. The method of claim 7 , wherein the second metal silicide member contacts one of the two sidewall layers.

9. The method of claim 1 , wherein the dielectric material layer is formed using at least one of a high-aspect-ratio process, a spin coating process, and a flowable chemical vapor deposition process.

10. The method of claim 1 , wherein an excess portion of the dielectric material layer that is positioned higher than the first gate structure is removed for forming the dielectric layer after the annealing process has been performed on the dielectric material layer.

11. The method of claim 10 , wherein the excess portion of the dielectric material layer is removed using at least one of a polishing process and an etch-back process.

12. The method of claim 1 , further comprising: forming a source region and a drain region at two opposite sides of the second gate structure, wherein the second metal silicide member is formed on one of the source region and the drain region after the annealing process has been performed.

13. The method of claim 1 , wherein the second metal silicide member is formed after the annealing process has been performed and is positioned between the second gate structure and the portion of the dielectric layer.

14. The method of claim 1 , wherein the second metal silicide member is formed after the annealing process has been performed, and wherein the second gate structure is positioned between the second metal silicide member and the portion of the dielectric layer.

15. The method of claim 1 , wherein the preliminary structure has fewer material layers than the first gate structure.

16. The method of claim 15 , wherein a height of the preliminary structure is equal to a height of the first gate structure.

17. The method of claim 1 , wherein the second gate structure is formed after the annealing process has been performed.

18. The method of claim 1 , wherein the second gate structure has fewer material layers than the first gate structure.

19. The method of claim 1 , wherein the second gate structure is spaced from the portion of the dielectric layer.

20. A method for manufacturing a semiconductor device, the method comprising:
preparing a stacked structure;
processing the stacked structure to form a first gate structure and a preliminary structure;
forming a dielectric material layer that covers at least the first gate structure;
forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure;
performing an annealing process on at least one of the dielectric material layer and the dielectric layer;
processing the preliminary structure to form a second gate structure; and
after the annealing process has been performed, forming a metal silicide member on an active region associated with the second gate structure, wherein the metal silicide member directly contacts the portion of the dielectric layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zou Lujun
• Yang Yun
• Li Shaobin
• Chiu Shengfen

Classifications

• H10D64/668

  the layer being a silicide, e.g. TiSi2 · CPC title

• H10D64/035 Primary

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H01L21/28273

  Electricity · mapped topic

• H01L27/11536

  Electricity · mapped topic

• H01L29/4975

  Electricity · mapped topic