Semiconductor device

Patent metadata

Field	Value
Publication number	US-9418986-B2
Application number	US-201213589160-A
Country	US
Kind code	B2
Filing date	Aug 19, 2012
Priority date	Aug 26, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first chip mounting portion;
a first conductor lead portion;
a first semiconductor chip having a first main surface, and a first back surface opposite to the first main surface and bonded to the first chip mounting portion; and
a sealing portion sealing therein the first semiconductor chip, and at least a part of each of the first chip mounting portion and the first conductor lead portion,
wherein the first semiconductor chip is formed with a first MOSFET and a second MOSFET which have respective drains thereof electrically coupled to each other, and respective gates thereof electrically coupled to each other,
wherein the first MOSFET is formed in a first region of the first main surface of the first semiconductor chip, and the second MOSFET is configured to detect a current flowing in the first MOSFET and is formed in a second region of the first main surface of the first semiconductor chip,
wherein the second region has an area smaller than that of the first region,
wherein a first gate pad electrically coupled to the gates of the first and second MOSFETs, first and second source pads electrically coupled to a source of the first MOSFET, and a third source pad electrically coupled to a source of the second MOSFET are formed over the first main surface of the first semiconductor chip,
wherein a drain electrode electrically coupled to the drains of the first and second MOSFETs is formed over the first back surface of the first semiconductor chip,
wherein the first and second source pads are electrically coupled to the first conductor lead portion via a first conductor plate,
wherein the first and second source pads of the first semiconductor chip are constructed to output a current flowing in the first MOSFET, and the third source pad is constructed to sense a source voltage of the first MOSFET,
wherein a first source wire is formed over the first and second source pads, and a second source wire is formed over the third source pad,
wherein the second source wire has one end coupled to the first source wire via a coupled portion, and
wherein, in a plan view, the third source pad is disposed such that it does not overlap with the first conductor plate, and the coupled portion of the second source wire and the first source wire is disposed such that it overlaps with the first conductor plate, such that a resistance between the first conductor plate and the first and second source pads is a constant value which is independent of a bonding displacement of the first conductor plate with respect to the first and second source pads.

2. The semiconductor device according to claim 1 ,
wherein, in the first main surface of the first semiconductor chip, the second source wire is formed in a same layer as that of the first source wire, and is formed in a region other than the first and second regions.

3. The semiconductor device according to claim 2 ,
wherein the first source wire and the second source wire are integrally formed, and are separated by a slit between the first source wire and the second source wire, and
wherein, in a plan view, an end portion of the slit is disposed at a position which overlaps with the first conductor plate.

4. The semiconductor device according to claim 3 ,
wherein the first conductor plate is a metal plate.

5. The semiconductor device according to claim 4 ,
wherein the first conductor plate is formed of copper, a copper alloy, aluminum, or an aluminum alloy.

6. The semiconductor device according to claim 5 ,
wherein the third source pad is electrically coupled to the source region of the first MOSFET formed in the first region via the second source wire and the first source wire.

7. The semiconductor device according to claim 6 , further comprising:
a second chip mounting portion;
a second semiconductor chip having a second main surface, and a second back surface opposite to the second main surface and bonded to the second chip mounting portion,
wherein the second semiconductor chip and at least a part of the second chip mounting portion are sealed in the sealing portion,
wherein the second semiconductor chip is formed with a control circuit for controlling the first and second MOSFETs,
wherein first, second, and third pads are formed over the second main surface of the second semiconductor chip, and
wherein the first gate pad is electrically coupled to the first pad of the second semiconductor chip via a first wire, the second source pad is electrically coupled to the second pad of the second semiconductor chip via a second wire, and the third source pad is electrically coupled to the third pad of the second semiconductor chip via a third wire.

8. The semiconductor device according to claim 7 ,
wherein the first MOSFET is configured to be controlled in accordance with a current flowing in the second MOSFET.

9. The semiconductor device according to claim 8 ,
wherein the control circuit includes:
a first drive circuit coupled to the first pad in the second semiconductor chip to supply a gate signal to the gates of the first and second MOSFETs; and
a first circuit coupled to the second and third pads in the second semiconductor chip and configured to control a current flowing in the second MOSFET such that an input voltage of the second pad and an input voltage of the third pad are the same.

Assignees

• Uno Tomoaki
• Onaya Yoshitaka
• Kato Hirokazu
• Kudo Ryotaro
• Saikusa Koji
• Renesas Electronics Corp

Inventors

• Uno Tomoaki
• Onaya Yoshitaka
• Kato Hirokazu
• Kudo Ryotaro
• Saikusa Koji

Classifications

• H10D84/839

  comprising VDMOS · CPC title

• H10D84/83125

  the IGFETs characterised by having shared source or drain regions · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/07653

  changes in shapes · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title