Redistribution layers for microfeature workpieces, and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9418970-B2
Application number	US-201514984354-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Aug 30, 2006
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

First claim

I claim:

1. A semiconductor device assembly, comprising:
a first semiconductor die including an integrated circuit and a conductive trace operably coupled to the integrated circuit;
a second semiconductor die attached to the first die and having no integrated circuit;
a first via connected to the conductive trace and extending through the first die; and
a second via extending through the second die, wherein the first and second vias join with one another at a location between the first and second dies.

2. The semiconductor device assembly of claim 1 , further comprising a first conductive cap on the first via, and a second conductive cap on the second via and connected to the first conductive cap.

3. The semiconductor device assembly of claim 1 wherein the second die comprises a silicon substrate and an adhesive material on an outer surface of the silicon substrate, wherein the adhesive material directly attaches the silicon substrate to the first die.

4. The semiconductor device assembly of claim 3 wherein the first die comprises a semiconductor substrate, and an adhesive material on an outer surface of the semiconductor substrate and attached to the adhesive material of the second die.

5. The semiconductor device assembly of claim 1 wherein the second via includes a protrusion projecting toward the first via and attached thereto.

6. The semiconductor device assembly of claim 5 wherein the first via includes a protrusion attached to the protrusion of the second via.

7. The semiconductor device assembly of claim 6 , further comprising a conductive cap between the protrusion of the first die and the protrusion of the second die.

8. The semiconductor device assembly of claim 1 wherein:
the first die includes a first outer surface;
the first via extends beyond the first outer surface;
the second die includes a second outer surface facing the first outer surface; and
the second via extends beyond the second outer surface.

9. A semiconductor device assembly, comprising first and second semiconductor dies attached to one another and each including—
a semiconductor substrate;
a via extending entirely through the semiconductor substrate and attached to the via of the other die; and
a conductive structure coupled to the via,
wherein the first die includes an integrated circuit and the second die does not include an integrated circuit, and wherein the integrated circuit of the first die is electrically coupled to the via and the conductive structure of each of the first and second dies.

10. The semiconductor device assembly of claim 9 wherein each semiconductor substrate comprises a silicon substrate, and wherein the integrated circuit is formed in the silicon substrate of the first die.

11. The semiconductor device assembly of claim 9 wherein the semiconductor substrate of the second die comprises a bare silicon substrate.

12. The semiconductor device assembly of claim 9 wherein the via of each of the first and second dies includes a protrusion projecting from an outer surface of the semiconductor substrate and attached to the protrusion of the other via.

13. The semiconductor device assembly of claim 9 wherein each of the first and second dies further includes an adhesive material attached to the adhesive material of the other die.

14. The semiconductor device assembly of claim 13 wherein each via is separated from the adhesive material of the other die.

15. The semiconductor device assembly of claim 9 , further comprising:
a first conductive feature on the via of the first die; and
a second conductive feature on the via of the second die, wherein the second conductive feature is connected to the first conductive feature at a location between the first and second vias.

16. A semiconductor device package, comprising:
a first semiconductor die including a semiconductor substrate and a plurality of first vias extending therethrough; and
a second semiconductor die stacked on the first semiconductor die, the second semiconductor including a semiconductor substrate and a plurality of second vias extending therethough, wherein the second vias are aligned with and connected to corresponding ones of the first vias,
wherein of one the first and second semiconductor dies includes an operable microfeature device and the other does not.

17. The semiconductor device package of claim 16 wherein the operable microfeature device is an integrated circuit formed in the semiconductor substrate of the first die.

18. The semiconductor device package of claim 16 wherein the operable microfeature device includes at least one of an integrated circuit, a capacitor, and a sensing element, but does not include bond pads, conductive lines, or vias.

19. The semiconductor device package of claim 16 wherein each of the first vias projects beyond the semiconductor substrate of the first die and toward a corresponding one of the second vias.

20. The semiconductor device package of claim 19 wherein each of the second vias projects beyond the semiconductor substrate of the second die and toward a corresponding one of the first vias.

Assignees

• Micron Technology Inc

Inventors

• Pratt David

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title