Integrated circuit chip assembled on an interposer

Patent metadata

Field	Value
Publication number	US-9418954-B2
Application number	US-201514659680-A
Country	US
Kind code	B2
Filing date	Mar 17, 2015
Priority date	Mar 19, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

First claim

The invention claimed is:

1. A device, comprising:
a chip assembled on an interposer;
an electrically-insulating layer coating an upper surface of the interposer around the chip;
first metal lines running on the upper surface of the interposer and arranged between conductive elements of connection to the chip, at least one end of each first metal line extending beyond a projection of the chip on the interposer;
a thermally-conductive via connecting said at least one end to a heat sink supported at an upper surface of the device; and
wherein the conductive elements of connection to the chip and the first metal lines are made of a same first material and have a same thickness.

2. The device of claim 1 , wherein extremities of each first metal line extend outside a projection of the chip on the interposer.

3. The device of claim 1 , wherein a width of each of the first lines is smaller than a width of said at least one corresponding end.

4. The device of claim 1 , wherein the first material is copper.

5. The device of claim 1 , wherein each conductive element of connection to the chip is connected by a solder material to a conductive element of connection to the corresponding interposer formed on the chip.

6. The device of claim 5 , wherein second metal lines run on the chip between said elements of connection to the interposer, the second metal lines being thermally connected to the first metal lines by a solder material.

7. The device of claim 6 , wherein the conductive elements of connection to the interposer and the second metal lines are made of a same second material and have a same thickness.

8. The device of claim 1 , wherein an electrically-insulating material fills free space between the chip and the interposer.

9. The device of claim 7 , wherein the second material is copper.

10. A device, comprising:
an integrated circuit chip having a first surface including first electrical connection pads and first conductive lines;
an interposer having a second surface including second electrical connection pads and second conductive lines;
wherein the integrated circuit chip is mounted to the interposer with the first and second electrical connection pads electrically connected to each other and the first and second conductive lines electrically connected to each other;
wherein the second conductive lines extend along the second surface to an end region positioned beyond a projection of the integrated circuit chip on the second surface of the interposer;
an electrically-insulating layer coating an upper surface of the interposer around the chip;
an insulating body surrounding the integrated circuit chip and having a top surface;
a heat sink member mounted to the top surface of the insulating body; and
a via extending through the insulating body to thermally connect the end region of the second conductive line to a bottom surface of the heat sink member.

11. The device of claim 10 , wherein the bottom surface of heat sink member is mounted adjacent a third surface of the integrated circuit chip, said third surface opposed to said first surface.

12. The device of claim 10 , wherein a width of the second conducting line is smaller than a width of said end region.

13. The device of claim 10 , wherein a solder material electrically connects the first and second electrical connection pads to each other and electrically connects the first and second conductive lines to each other.

14. The device of claim 10 , where the first and second conductive lines extend between pairs of first and second electrical connection pads, respectively.

15. A device, comprising:
a chip assembled on an interposer;
an electrically-insulating layer coating an upper surface of the interposer around the chip;
first metal lines running on the upper surface of the interposer and arranged between conductive elements of connection to the chip, at least one end of each first metal line extending beyond a projection of the chip on the interposer;
a thermally-conductive via connecting said at least one end to a heat sink supported at an upper surface of the device;
wherein each conductive element of connection to the chip is connected by a solder material to a conductive element of connection to the corresponding interposer formed on the chip; and
wherein second metal lines run on the chip between said elements of connection to the interposer, the second metal lines being thermally connected to the first corresponding metal lines by a solder material.

16. The device of claim 15 , wherein a second end of each first metal line disposed opposite the at least one first end extends outside a projection of the chip on the interposer.

17. The device of claim 15 , wherein a width of each of the at least one ends is larger than a width of the corresponding first metal line.

18. The device of claim 15 , wherein the first material is copper.

19. The device of claim 15 , wherein the conductive elements of connection to the interposer and the second metal lines are made of a same second material and have a same thickness.

20. The device of claim 19 , wherein the second material is copper.

21. The device of claim 15 , wherein an electrically-insulating material fills free space between the chip and the interposer.

Assignees

• St Microelectronics Sa
• St Microelectronics Crolles 2 Sas

Inventors

• Bar Pierre
• Taluy Alisee
• Kokshagina Olga

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/07336

  Soldering or alloying · CPC title