Power line structure for semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-9418936-B2
Application number	US-201615070317-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Jan 27, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor apparatus has one or more semiconductor chips. The semiconductor apparatus may include a power supply pad; power lines disposed on one side of the power supply pad, and including a first power line and a second power line; and connection lines connecting the power supply pad and the power lines. The connection lines may include a plurality of first connection lines connecting the power supply pad and the first power line, and a plurality of second connection lines connecting the power supply pad and the second power line, and disposed between the first connection lines. One or more pair of adjacent first connection lines may have a connection part by which the pair of adjacent first connection lines are connected with each other.

First claim

What is claimed is:

1. A semiconductor apparatus comprising:
power supply pads including a first power supply pad which is configured to supply a first power and a second power supply pad which is configured to supply a second power;
power lines disposed on one side of the power supply pads, and including a first power line and a second power line; and
connection lines including a first connection line module which connects the first power supply pad and the first power line with a first connection section, and a second connection line module which connects the second power supply pad and the second power line with a second connection section,
wherein the first connection line module is formed such that a width of a region which crosses with the first power line is larger than a width of a region which crosses with the second power line, and
wherein the second connection line module is formed such that a width of a region which crosses with the second power line is larger than a width of a region which crosses with the first power line.

2. The semiconductor apparatus according to claim 1 , wherein the connection lines further include a first dummy connection line which connects the first power supply pad and the second power line, and a second dummy connection line which connects the second power supply pad and the first power line.

3. The semiconductor apparatus according to claim 1 ,
wherein the first power line is configured to supply the first power to a first internal circuit the second power line is configured to supply the second power to the first internal circuit, and
wherein the power lines further include a third power line which is configured to supply the first power to a second internal circuit and a fourth power line which is configured to supply the second power to the second internal circuit.

4. The semiconductor apparatus according to claim 3 ,
wherein the first connection line module further has a third connection section which extends from the first connection section and connects the first power supply pad and the third power line, and
wherein the second connection line module further has a fourth connection section which extends from the second connection section and connects the second power supply pad and the fourth power line.

5. The semiconductor apparatus according to claim 3 , wherein the second internal circuit is a circuit which requires more power than the first internal circuit.

6. The semiconductor apparatus according to claim 5 ,
wherein the first internal circuit is a trigger unit of an electrostatic protection circuit, and
wherein the second internal circuit is a circuit in a memory bank.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Hwan
• Choi Won John

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/427 Primary

  Power or ground buses · CPC title