Semiconductor device

Patent metadata

Field	Value
Publication number	US-9418910-B2
Application number	US-201214385311-A
Country	US
Kind code	B2
Filing date	Jul 5, 2012
Priority date	Jul 5, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A circuit pattern is bonded to a top surface of a ceramic substrate. A cooling body is bonded to an undersurface of the ceramic substrate. An IGBT and a FWD are provided on the circuit pattern. A coating film covers a junction between the ceramic substrate and the circuit pattern, and a junction between the ceramic substrate and the cooling body. A mold resin seals the ceramic substrate, the circuit pattern, the IGBT, the FWD, the cooling body, and the coating film etc. The ceramic substrate has higher thermal conductivity than the coating film. The coating film has lower hardness than the mold resin and alleviates stress applied from the mold resin to the ceramic substrate. The circuit pattern and the cooling body includes a groove contacting the mold resin without being covered with the coating film.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an insulating substrate having first and second main surfaces facing each other;
a circuit pattern bonded to the first main surface of the insulating substrate;
a cooling body bonded to the second main surface of the insulating substrate;
a semiconductor element on the circuit pattern;
a coating film covering a junction between the insulating substrate and the circuit pattern, and a junction between the insulating substrate and the cooling body; and
a resin sealing the insulating substrate, the circuit pattern, the semiconductor element, the cooling body, and the coating film,
wherein the insulating substrate has higher thermal conductivity than the coating film,
the coating film has lower hardness than the resin and alleviates stress applied from the resin to the insulating substrate, and
at least one of the circuit pattern and the cooling body includes a groove or a protrusion contacting the resin without being covered with the coating film.

2. The semiconductor device according to claim 1 , wherein an undersurface electrode of the semiconductor element is bonded to a top surface of the circuit pattern via solder, and
the coating film surrounds a region in which the semiconductor element is mounted on the top surface of the circuit pattern.

3. The semiconductor device according to claim 1 , wherein a lateral width of the cooling body is equal to or greater than a lateral width of the insulating substrate.

Assignees

• Miyamoto Noboru
• Yoshimatsu Naoki
• Mitsubishi Electric Corp

Inventors

• Miyamoto Noboru
• Yoshimatsu Naoki

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/655

  of outermost layers of multilayered strap connectors, e.g. material of a coating · CPC title

• H10W72/652

  comprising metals or metalloids, e.g. silver · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title