Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Patent metadata

Field	Value
Publication number	US-9418721-B2
Application number	US-201414159605-A
Country	US
Kind code	B2
Filing date	Jan 21, 2014
Priority date	Jan 21, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

First claim

The invention claimed is:

1. An apparatus comprising:
a memory storing a performance characteristic determined from a relationship between two or more of: a bit error rate, a programming pulse width, a history based predictive performance parameter, a temperature, a coding scheme for data, or a voltage level associated with the memory, wherein the programming pulse width is a length of a pulse used to write the data; and
a controller in communication with the memory, the controller configured to:
determine the performance characteristic;
manage a write operation to the memory based on the performance characteristic and based on a number of data flips that are to be performed in response to a determination that the temperature is above a first threshold value, and wherein the number of data flips is based on an exclusive-OR operation; and
determine the programming pulse width and subsequently perform one of: a long write operation in response to a determination that the number of data flips is greater than a second threshold value or a short write operation in response to a determination that the number of data flips is less than the second threshold value.

2. The apparatus of claim 1 , wherein the controller is further configured to vary the programming pulse width.

3. The apparatus of claim 1 , wherein the performance characteristic is determined from the relationship between the bit error rate and one or more of: the programming pulse width, the history based predictive performance parameter, the temperature, the coding scheme, and the voltage level associated with the memory.

4. The apparatus of claim 1 , wherein the memory is a spin transfer torque magnetoresistive random-access memory (STT-MRAM).

5. The apparatus of claim 1 , further comprising a temperature sensor configured to detect the temperature associated with the memory and to communicate the temperature to the controller.

6. A non-transitory computer readable storage medium comprising instructions, that when executed by a processor, cause the processor to:
determine a performance characteristic that includes relationship information relating to a bit error rate and relating to at least one of a programming pulse width, a temperature, history-based predictive performance parameter, a coding scheme for data, or a voltage level also associated with a memory, wherein the programming pulse width is a length of a pulse used to write the data;
store the performance characteristic;
use the performance characteristic and a number of data flips to manage a write operation associated with the memory, wherein the number of data flips is performed in response to a determination that the temperature is above a first threshold value, wherein the number of data flips is based on an exclusive-OR operation; and
determine the programming pulse width and subsequently perform one of: a long write operation in response to a determination that the number of data flips is greater than a second threshold value or a short write operation in response to a determination that the number of data flips is less than the second threshold value.

7. An apparatus comprising:
a memory storing a performance characteristic determined from a relationship between a bit error rate, a programming pulse width, and one or more of a history based predictive performance parameter, a temperature, a coding scheme for data, or a voltage level associated with the memory, wherein the programming pulse width is a length of a pulse used to write the data; and
a controller in communication with the memory, the controller configured to:
determine the performance characteristic;
store the performance characteristic; and
manage a write operation to the memory using the stored performance characteristic, wherein using the stored performance characteristic includes determining whether to perform at least one of a long write operation, a sequence of short write operations, or a single short write operation.

8. The apparatus of claim 3 , wherein managing the write operation, the controller is further configured to use the stored performance characteristic in the memory that is based on the relationship between the bit error rate and the programming pulse width.

9. The apparatus of claim 1 , wherein the controller is further configured to use the performance characteristic to vary the coding scheme for data to be written to the memory.

10. The apparatus of claim 1 , wherein the controller is configured to determine the performance characteristic at runtime.

11. The apparatus of claim 1 , wherein the controller is configured to determine the performance characteristic at test time.

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Guo Xiaochen
• Hunter Hillery C
• Rivers Jude A
• Srinivasan Vijayalakshmi

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title