Optical and thermal interface for photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-9417411-B2
Application number	US-201514611392-A
Country	US
Kind code	B2
Filing date	Feb 2, 2015
Priority date	Feb 21, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Described herein are photonic systems and devices including a optical interface unit disposed on a bottom side of a photonic integrated circuit (PIC) to receive light from an emitter of the PIC. A top side of the PIC includes a flip-chip interface for electrically coupling the PIC to an organic substrate via the top side. An alignment feature corresponding to the emitter is formed with the emitter to be offset by a predetermined distance value; because the emitter and the alignment feature are formed using a shared processing operation, the offset (i.e., predetermined distance value) may be precise and consistent across similarly produced PICs. The PIC comprises a processing feature to image the alignment feature from the bottom side (e.g., a hole). A heat spreader layer surrounds the optical interface unit and is disposed on the bottom side of the PIC to spread heat from the PIC.

First claim

The invention claimed is:

1. An apparatus comprising:
an optical interface unit;
a photonic integrated circuit (PIC), including:
a bottom side, wherein the optical interface unit is disposed on the bottom side;
a top side including a flip-chip interface for electrically coupling the PIC to an organic substrate via the top side;
an emitter to emit light through the PIC out of the bottom side to the optical interface unit; and
an alignment feature corresponding to the emitter and formed with the emitter to be offset by a predetermined distance value, wherein the PIC comprises a processing feature to image the alignment feature from the bottom side; and

a heat spreader layer surrounding the optical interface unit and disposed on the bottom side of the PIC to spread heat from the PIC.

2. The apparatus of claim 1 , wherein the processing feature of the PIC comprises a hole etched to provide a line of sight to the alignment feature via the bottom side of the PIC.

3. The apparatus of claim 2 , wherein the hole comprises an air gap and is further aligned with one or more components of the PIC to provide thermal isolation to the one or more components.

4. The apparatus of claim 2 , further comprising:
a spacer material to fill the hole of the PIC.

5. The apparatus of claim 4 , wherein the spacer material is further disposed in a hole of the heat spreader layer including the optical interface unit to secure the optical interface unit within the heat spreader layer.

6. The apparatus of claim 1 , further comprising:
a structure for aligning an optical connector to the optical interface unit.

7. The apparatus of claim 6 , wherein the structure for aligning the optical connector to the optical interface unit is separate from the heat spreader layer, the PIC, and the optical interface unit.

8. The apparatus of claim 6 , wherein the structure comprises recessed processing features included in the heat spreader layer corresponding to one or more features of the optical connector.

9. The apparatus of claim 6 , wherein the structure comprises recessed processing features included in the optical interface unit corresponding to one or more features of the optical connector.

10. The apparatus of claim 1 , wherein the offset between the emitter and the corresponding alignment feature comprises at least one of a horizontal offset, a vertical offset, or a depth offset.

11. The apparatus of claim 1 , wherein the optical interface unit comprises a structure for passively aligning an optical input/output (I/O) interface of an external connector to the emitter of the PIC.

12. The apparatus of claim 1 , wherein the optical interface unit comprises a lens unit.

13. The apparatus of claim 12 , wherein the lens unit comprises a lens array.

14. The apparatus of claim 1 , further comprising:
an electrical integrated circuit (IC) including control or driver circuity for one or more devices of the PIC and an electrical input/output (I/O) interface; and
an organic substrate.

15. The apparatus of claim 14 , wherein the organic substrate is to communicatively couple the PIC and the electrical IC, wherein the electrical I/O interface of the electrical IC and the flip-chip interface of the PIC are disposed on opposing sides of the organic substrate.

16. The apparatus of claim 14 , wherein the electrical IC is disposed underneath the PIC, and the electrical I/O interface is disposed onto the PIC to communicatively coupled the electrical I/C to the PIC.

17. A method comprising:
forming an emitter and a corresponding alignment feature on a top side of a photonic integrated circuit (PIC) to be offset by a predetermined distance value, wherein the alignment feature can be imaged from a bottom side of the PIC;
coupling the top side of the PIC to an organic substrate via flip-chip interconnects;
passively aligning an optical interface unit to the emitter using the alignment feature to place the optical interface unit on the bottom side of the PIC; and
disposing a heat spreading material layer on the PIC, the optical interface unit included in the heat spreading material layer.

18. The method of claim 17 , further comprising:
etching a hole on the bottom side of the PIC such that the alignment feature is viewable via the hole.

19. The method of claim 18 , further comprising:
etching an additional one or more holes on the bottom side of the PIC to thermally isolate one or more optical components of the PIC.

20. The method of claim 18 , further comprising:
depositing a spacer material in the etched hole to surround the optical interface unit within the hole.

21. The method of claim 17 , further comprising:
forming one or more features in the heat spreading material layer to correspond to an external optical connector.

22. The method of claim 17 , further comprising:
forming one or more features in the optical interface to correspond to an external optical connector.

23. The method of claim 17 , wherein passively aligning the optical interface unit to the emitter using the alignment feature includes at least one of a horizontal adjustment to a placement of the optical interface unit, a vertical adjustment to the placement of the optical interface unit, a depth adjustment to the placement of the optical interface unit, or a tilt adjustment to the optical interface unit.

Assignees

• Aurrion Inc

Inventors

• Fish Gregory Alan
• Koch Brian R

Classifications

• G02B6/12004

  Combinations of two or more optical elements · CPC title

• G02B6/4219

  Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor · CPC title

• G02B6/4232

  using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072) · CPC title

• Y10T29/49117

  Conductor or circuit manufacturing · CPC title

• G02B6/132

  by deposition of thin films · CPC title