Semiconductor package including an embedded circuit component within a support structure of the package

US9414497B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9414497-B2
Application numberUS-201514815184-A
CountryUS
Kind codeB2
Filing dateJul 31, 2015
Priority dateNov 15, 2011
Publication dateAug 9, 2016
Grant dateAug 9, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a support structure including a first surface, a second surface opposing the first surface, and a cavity extending at least partially between the first and second surfaces; a semiconductor device supported by the support structure; a circuit element disposed in the cavity, the circuit element being electrically connected to the semiconductor device; an electrically non-conductive filling material disposed within the cavity so as to fill the cavity and at least partially surround the circuit element; a build-on layer disposed over the first surface or the second surface of the support structure including the cavity, the build-on layer comprising an insulating material or a dielectric material; a via formed within the build-on layer that extends to at least a portion of a conductive terminal end of the circuit element; a conductive material layer disposed over at least a portion of the build-on layer that extends within the via and contacts the conductive terminal end of the circuit element; and a second conductive material layer disposed between the build-on layer and the first surface or the second surface of the support structure, wherein each of the conductive material layer and the second conductive material layer provides an electrical path between circuit components of the semiconductor device, and the second conductive material layer extends within side wall portions of the cavity in the support structure. 2. The apparatus of claim 1 , wherein the circuit element is operable to substantially block direct current output by the semiconductor device or another semiconductor device. 3. The apparatus of claim 1 , wherein the circuit element is disposed in the cavity in an orientation such that a longitudinal axis of the circuit element is substantially perpendicular to the first surface or the second surface of the support structure. 4. The apparatus of claim 1 , wherein the cavity includes at least one tapered wall, and the circuit element is aligned within the cavity in an orientation such that a longitudinal axis of the circuit element is tilted within the cavity and non-perpendicular to the first surface or the second surface of the support structure. 5. The apparatus of claim 1 , further comprising: a platform disposed within the cavity to support the circuit element. 6. The apparatus of claim 5 , wherein the platform includes an opening that extends through the platform to the second surface of the support structure. 7. The apparatus of claim 1 , wherein the second conductive material layer provides an electrical path for circuit components that are not connected with the circuit element. 8. The apparatus of claim 1 , further comprising: an embedded conductive material layer within the support structure that provides an electrical path between circuit components of the semiconductor device. 9. The apparatus of claim 1 , further comprising: a plurality of build-on layers disposed in a vertically stacked manner upon the first surface or the second surface of the support structure; and a third conductive material layer disposed between at least a first build-on layer and a second build-on layer vertically stacked on the first build-on layer, wherein the third conductive material layer provides an electrical path between circuit components of the semiconductor device. 10. The apparatus of claim 1 , further comprising: a first fill material disposed within the cavity, the first fill material including an opening formed within the first fill material that extends at least partially the longitudinal dimension of the first fill material, wherein the circuit element is disposed within the opening of the first fill material; and a second fill material disposed within the opening of the first fill material that at least partially surrounds the circuit element. 11. An apparatus comprising: a support structure including a first surface, a second surface opposing the first surface, and a cavity extending at least partially between the first and second surfaces; a semiconductor device supported by the support structure; a circuit element disposed in the cavity, the circuit element being electrically connected to the semiconductor device; and an electrically non-conductive filling material disposed within the cavity so as to fill the cavity and at least partially surround the circuit element; wherein the cavity includes at least one tapered wall, and the circuit element is aligned within the cavity in an orientation such that a longitudinal axis of the circuit element is tilted within the cavity and non-perpendicular to the first surface or the second surface of the support structure. 12. The apparatus of claim 11 , wherein the circuit element is operable to substantially block direct current output by the semiconductor device or another semiconductor device. 13. The apparatus of claim 11 , further comprising: a platform disposed within the cavity to support the circuit element. 14. The apparatus of claim 13 , wherein the platform includes an opening that extends through the platform to the second surface of the support structure. 15. The apparatus of claim 11 , further comprising a conductive material layer formed over portions of the first surface or the second surface of the support structure, the conductive material layer further extending within side wall portions of the cavity in the support structure so as to provide an electrical path for circuit components of the apparatus that are not connected with the circuit element. 16. The apparatus of claim 15 , further comprising: a build-on layer disposed over the first surface or the second surface of the support structure including the filled cavity, the build-on layer comprising an insulating material or a dielectric material.

Assignees

Inventors

Classifications

  • associated with surface mounted components · CPC title

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • Electrically connected to another device · CPC title

  • Involving several components · CPC title

  • Conductive through-holes or vias · CPC title

Patent family

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Frequently asked questions

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What does patent US9414497B2 cover?
An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling m…
Who is the assignee on this patent?
Cisco Tech Inc
What technology area does this patent fall under?
Primary CPC classification H05K1/183. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).