Wireless transmission synchronization using a power line signal

Patent metadata

Field	Value
Publication number	US-9413519-B2
Application number	US-201514681337-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 11, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A gateway may be configured to synchronize transmissions of a plurality of faulted circuit indicators (FCIs). The gateway may determine a time delay from a zero crossing of a power line signal and obtain network information from the at least one FCI from the plurality of FCIs. The gateway may identify a proximate FCI that is closest to a gateway based on at least one link parameter, and assign the determined time delay to the proximate FCI. The gateway may receive confirmations that at least one FCI received the determined time delay, and has synchronized transmissions based on the determined time delay and the zero crossings of the power signal.

First claim

What is claimed is:

1. A method for synchronizing transmissions of a plurality of faulted circuit indicators (FCIs), comprising:
determining a time delay from a zero crossing of a power line signal;
obtaining network information from at least one FCI from the plurality of FCIs;
identifying a proximate FCI, which is closest to a gateway based on at least one link parameter;
assigning the determined time delay to the proximate FCI; and
receiving confirmations that at least one FCI received the determined time delay, and has synchronized transmissions based on the determined time delay and the zero crossings of the power signal.

2. The method of claim 1 , wherein obtaining network information from the plurality of FCIs further comprises:
transmitting a multicast request to the plurality of FCIs for an address and a hop count; and
receiving the address and the hop count from the plurality of FCIs in response to the multicast request.

3. The method of claim 2 , wherein transmitting the multicast request to the plurality of FCIs transitions at least one FCI from a power savings state to an active state.

4. The method of claim 1 , wherein identifying the proximate FCI further comprises:
determining the nearest FCI based on at least one of signal strength or time delays.

5. The method of claim 1 , wherein determining the time delay comprises:
calculating the time delay to reduce interference with the plurality of FCI transmissions caused by the power line signal.

6. A gateway, comprising:
a communication interface;
a memory configured to store instructions; and
a processor, coupled to the communications interface and memory, configured to execute the instructions stored in the memory to:
determine a time delay from a zero crossing of a power line signal,
obtain network information from the at least one Faulted Circuit Indicator (FCI) from the plurality of FCIs,
identify a proximate FCI, which is closest to a gateway based on at least one link parameter,
assign the determined time delay to the proximate FCI, and
receive confirmations that at least one FCI received the determined time delay, and has synchronized transmissions based on the determined time delay and the zero crossings of the power signal.

7. The gateway of claim 6 , wherein the instructions to obtain network information from the plurality of FCIs comprises instructions configuring the processor to:
transmit a multicast request to the plurality of FCIs for an address and a hop count; and
receive the address and the hop count from the plurality of FCIs in response to the multicast request.

8. The gateway of claim 7 , wherein the instructions to transmit the multicast request to the plurality of FCIs comprises instructions configuring the processor to transition at least one FCI from a power savings state to an active state.

9. The gateway of claim 6 , wherein the instructions to identify the proximate FCI comprises instructions configuring the processor to:
determine the nearest FCI based on at least one of signal strength or time delays.

10. The gateway of claim 6 , wherein the instructions to determine the time delay comprises instructions configuring the processor to:
calculate the time delay to reduce interference with the plurality of FCI transmissions caused by the power line signal.

11. A method to synchronize transmissions, comprising:
receiving a request for network information from a gateway;
transmitting network information in response to the received request;
receiving a time delay from an adjacent fault condition indicator (FCI) or gateway;
synchronizing transmissions according to the received time delay and a frequency based on zero crossings of a power line signal; and
providing fault condition information over the synchronized transmissions.

12. The method of claim 11 , further comprising:
transmitting a confirmation to the gateway that the time delay was received and the transmission are synchronized based on the received time delay and the zero crossings of the power line signal.

13. The method of claim 11 , further comprising:
determining whether the power line signal is available; and
transmitting the fault condition information at a frequency based on the zero crossings derived from the power line signal, when it is determined that the power line signal is available.

14. The method of claim 13 , wherein it is determined that the power line signal is not available, the method further comprises:
generating an internal clock signal based on the received time delay and the zero crossings of the power line signal; and
transmitting the fault condition information at a frequency derived from the internal clock signal.

15. The method of claim 11 , wherein the received request for network information is a multicast request, the method further comprising:
transitioning from a power savings state to an active state; and
transmitting directly to the gateway an address and a hop count.

16. The method of claim 11 , wherein providing the fault condition information over the synchronized transmissions comprises:
transmitting the fault condition information to the gateway through at least one FCI.

17. A faulted circuit indicator (FCI), comprising:
a power line sensor;
a digital interface coupled to the power line sensor;
a wireless communication interface;
a memory configured to store instructions;
a processor, coupled to the digital interface, the communications interface, and the memory, configured to execute the instructions stored in the memory to:
receive a request for network information from a gateway,
transmit network information in response to the received request,
receive a time delay from an adjacent FCI or gateway,
synchronize transmissions according to the received time delay and a frequency based on zero crossings of a power line signal, and
provide fault condition information over the synchronized transmissions; and

a backup power source coupled to the processor, the memory, the power line sensor, the digital interface, and the wireless communication interface.

18. The faulted circuit indicator of claim 17 , wherein the processor is configured to:
transmit a confirmation to the gateway that the time delay was received and the transmission are synchronized based on the received time delay and the zero crossings of the power line signal.

19. The faulted circuit indicator of claim 17 , wherein the processor is further configured to:
determine whether the power line signal is available; and
transmit the fault condition information at a frequency based on the zero crossings derived from the power line signal, when it is determined that the power line signal is available.

20. The faulted circuit indicator of claim 19 , wherein it is determined that the power line signal is not available, the processor is configured to:
generate an internal clock signal based on the received time delay and the zero crossings of the power line signal; and
transmit the fault condition information at a frequency derived from the internal clock signal.

21. The faulted circuit indicator of claim 17 , wherein the received request for network information is a multicast request, the processor is configured to:
transition from a power savings state to an active state; and
transmit directly to the gateway an address and a hop count.

22. The faulted circuit indicator of claim 17 , wherein the instructions for providing the fault condition inform

Assignees

• Thomas & Betts Int Llc
• Thomas & Betts Int

Inventors

• Khoshnood Bahman
• Dodds William J
• Delgado Camilo
• Bright Eugene
• Ocasio David

Classifications

• H02J13/1313

  using pulsed signals · CPC title

• G01R31/08

  Locating faults in cables, transmission lines, or networks · CPC title

• G01R31/086 Primary

  in power transmission or distribution networks, i.e. with interconnected conductors · CPC title

• H04L12/10

  Current supply arrangements · CPC title

• H04L7/0041 Primary

  Delay of data signal · CPC title