Method for clock calibration

Patent metadata

Field	Value
Publication number	US-9413359-B2
Application number	US-201514743174-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Dec 23, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A system may include a plurality of devices, wherein each device of the plurality of devices has a respective clock source. A first device of the plurality of devices may be configured to generate a first clock signal. A second device of the plurality of devices may be configured to generate a second clock signal, receive the first clock signal from the first device, and modify a first frequency of the first clock signal. The second device may be further configured to adjust a second frequency of the second clock signal dependent upon the modified first frequency of the first clock signal.

First claim

What is claimed is:

1. A system comprising:
a plurality of devices, wherein each device of the plurality of devices has a respective clock source;
wherein a first device of the plurality of devices is configured to generate a first clock signal;
wherein a second device of the plurality of devices is configured to:
generate a second clock signal;
receive the first clock signal from the first device;
modify a first frequency of the first clock signal; and
adjust a second frequency of the second clock signal dependent upon the modified first frequency of the first clock signal.

2. The system of claim 1 , wherein the first device is further configured to use a clock output of an inter-integrated circuit (I 2 C) interface to generate the first clock signal.

3. The system of claim 2 , wherein to modify the first frequency of the first clock signal, the second device is further configured to stretch the first clock signal.

4. The system of claim 1 , wherein the second device is further configured to generate a third clock signal with the first frequency and send the third clock signal to a third device of the plurality of devices.

5. The system of claim 4 , wherein the third device is configured to:
generate a fourth clock signal;
receive the third clock signal from the second device;
modify the first frequency of the third clock signal; and
adjust a fourth frequency of the fourth clock signal dependent upon the modified first frequency of the third clock signal.

6. The system of claim 1 , wherein to generate the first clock signal, the first device includes a crystal oscillator.

7. The system of claim 1 , wherein a respective supply voltage terminal of the first device is coupled to a positive terminal of a first power supply, and wherein a respective common mode voltage terminal of the second device is coupled to the positive terminal of the first power supply.

8. A method, comprising:
generating, by a first circuit, a first clock signal;
generating, by a second circuit, a second clock signal;
receiving, by the second circuit, the first clock signal from the first circuit;
modifying, by the second circuit, a first frequency of the first clock signal; and
adjusting, by the second circuit, a second frequency of the second clock signal dependent upon the modified frequency of the first clock signal.

9. The method of claim 8 , wherein the first circuit includes a clock output of an inter-integrated circuit (I 2 C) interface.

10. The method of claim 9 , wherein modifying the first frequency of the first clock signal further comprises stretching, by the second circuit, the first clock signal.

11. The method of claim 8 , further comprising sending, by the second circuit, the second clock signal to a third circuit.

12. The method of claim 11 , further comprising:
generating, by the third circuit, a third clock signal;
receiving, by the third circuit, the second clock signal from the second circuit;
modifying, by the third circuit, the second frequency of the second clock signal; and
adjusting, by the third circuit, a third frequency of the third clock signal dependent upon the modified second frequency of the second clock signal.

13. The method of claim 8 , wherein generating the first clock signal comprises using a crystal oscillator.

14. The method of claim 8 , further comprising:
supplying a voltage level at a power supply terminal of the first circuit; and
supplying the voltage level at a common mode terminal of the second circuit.

15. An apparatus, comprising:
an input circuit configured to receive a first clock signal;
a logic circuit configured to modify a frequency of the first clock signal; and
a clock circuit configured to generate a second clock signal dependent upon the modified frequency of the first clock signal.

16. The apparatus of claim 15 , wherein the input circuit is further configured to receive the first clock signal via an inter-integrated circuit (I 2 C) interface.

17. The apparatus of claim 16 , wherein to modify the frequency of the first clock signal, the logic circuit is further configured to stretch the first clock signal.

18. The apparatus of claim 17 , wherein the logic circuit is further configured to broadcast a command to at least one other device in response to receiving the first clock signal via the I 2 C interface.

19. The apparatus of claim 18 , wherein the command is broadcast via a second interface, wherein the second interface is different than the I 2 C interface.

20. The apparatus of claim 15 , wherein to generate the second clock signal dependent upon the modified frequency of the first clock signal, the clock circuit is further configured to use a counter circuit.

Assignees

• Apple Inc

Inventors

• Stirk Gary L

Classifications

• H02J7/865

  Battery or charger load switching, e.g. concurrent charging and load supply (H02J7/50 takes precedence) · CPC title

• G01R31/374

  with means for correcting the measurement for temperature or ageing · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03L7/00 Primary

  Automatic control of frequency or phase; Synchronisation · CPC title

• G06F13/4256

  using a clocked protocol · CPC title