Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US9412940B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9412940-B2 |
| Application number | US-201314418859-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 19, 2013 |
| Priority date | Aug 3, 2012 |
| Publication date | Aug 9, 2016 |
| Grant date | Aug 9, 2016 |
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A bipolar resistive switching device (RSM device, FIG. 35 ) comprises an electrically conductive bottom electrode (BE, FIG. 35 ); a stack of transition metal oxides layers (RSM, FIG. 35 ), a number of transition metal oxide layers (RSO, FIG. 35 ) being equal or greater than 2, the stack comprising: at least one MO x layer (RSOA, FIG. 35 ), at least one oxygen gettering layer NO y (RSOB, FIG. 35 ). The resistive switching device further comprises an electrically conductive top electrode (TE, FIG. 35 ).
Opening claim text (preview).
The invention claimed is: 1. A bipolar resistive switching device comprising: an electrically conductive bottom electrode; a stack of transition metal oxides layers, a number of transition metal oxide layers being equal or greater than 2, the stack comprising: at least one MOx layer, at least one oxygen gettering layer NO y ; and the resistive switching device further comprises an electrically conductive top electrode. 2. The switching device of claim 1 , wherein the oxygen gettering layer comprises a transition metal oxide taken from the list comprising: CrO y , TiO y , HfO y , NbO y . 3. The switching device of claim 2 , wherein a value of the stochiometric number y is in the range 0<y≦2. 4. The switching device of claim 1 , wherein values of the stochiometric number x is in the range 0<x≦2.5. 5. The switching device of claim 1 , wherein the metal M is taken from the list comprising: Cr, Ti, Hf, Ta, Nb. 6. The switching device of claim 1 wherein the stack of transition metal oxide layer further includes at least one layer of metal (INTE). 7. A circuit comprising 2 bipolar resistive switching devices as described in claim 1 , the 2 bipolar resistive switching devices being serially connected in such a way that their polarities are opposed. 8. A programming operation of the circuit of claim 7 , wherein each one of the voltage signals −5V≦V p1 ≦+5V, −5V≦V p2 ≦+5V, −5V≦V p3 ≦+5V are simultaneously applied to each one of the electrodes forming the circuit, causing the two bipolar resistive switching devices to simultaneously change resistive state.
Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way · CPC title
comprising metal oxide memory material, e.g. perovskites · CPC title
Read using current through the cell · CPC title
Electricity · mapped topic
Array wherein the access device being a diode · CPC title
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