Memory cells, methods of forming memory cells and methods of forming memory arrays

Patent metadata

Field	Value
Publication number	US-9412936-B2
Application number	US-201514854212-A
Country	US
Kind code	B2
Filing date	Sep 15, 2015
Priority date	Apr 11, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

First claim

We claim:

1. A memory cell, comprising at least two programmable material structures directly between a pair of electrodes; a first of the programmable material structures having a first edge that extends primarily along a first axis; a second of the programmable material structures having a second edge that is directly against the first edge, and that extends primarily along a second axis that intersects the first axis; and wherein:
the second programmable material structure is over the first programmable material structure;
the first edge is an upper edge of the first programmable material structure;
the second edge is a lower edge of the second programmable material structure;
the second material structure has an upper edge in opposing relation to its lower edge;
the memory cell includes a third programmable material structure that has a lower edge which is over the upper edge of the second programmable material structure;
the third programmable material structure has an upper edge in opposing relation to its lower edge; and
the memory cell includes a fourth programmable material structure that has a lower edge that is over and directly against the upper edge of the third programmable material structure.

2. The memory cell of claim 1 wherein the lower edge of the third programmable material structure is spaced from the upper edge of the second programmable material structure by a barrier material.

3. The memory cell of claim 1 wherein the lower edge of the third programmable material structure is directly against the upper edge of the second programmable material structure.

4. A memory cell, comprising:
a bottom electrode;
at least three programmable material plates over the bottom electrode; the programmable material plates defining at least two switching volumes; a first switching volume being configured to switch relatively rapidly between “A” and “B” memory states, and a second switching volume being configured to switch relatively slowly between “C” and “D” memory states; and
a top electrode over the programmable material plates.

5. The memory cell of claim 4 wherein the programmable material plates comprise:
a first programmable material plate supported edgewise over the bottom electrode, the first programmable material plate extending primarily along a first axis;
a second programmable material plate supported edgewise over the first programmable material plate, the second programmable material plate extending primarily along a second axis that intersects the first axis; the first and second programmable material plates directly contacting one another along a first interface; the first switching volume overlapping the first interface;
a third programmable material plate supported edgewise over the second programmable material plate, the third programmable material plate extending primarily along a third axis; and
a fourth programmable material plate supported edgewise over the third programmable material plate, the fourth programmable material plate extending primarily along a fourth axis that intersects the third axis; the third and fourth programmable material plates directly contacting one another along a second interface;
the second switching volume overlapping the second interface.

6. The memory cell of claim 5 wherein the third programmable material plate directly contacts the second programmable material plate.

7. The memory cell of claim 5 wherein the third programmable material plate is spaced from the second programmable material plate by a barrier material.

8. The memory cell of claim 5 wherein the second and third axes are a common axis.

9. The memory cell of claim 8 wherein the first and fourth axes are a common axis.

10. A method of forming a memory cell, comprising:
forming a bottom electrode over a supporting base;
forming at least three programmable material plates over the bottom electrode; the programmable material plates defining at least two switching volumes; a first switching volume being configured to switch relatively rapidly between “A” and “B” memory states, and a second switching volume being configured to switch relatively slowly between “C” and “D” memory states; and
forming a top electrode over the programmable material plates.

Assignees

• Micron Technology Inc

Inventors

• Liu Jun
• Zahurak John K

Classifications

• H01L45/144

  Electricity · mapped topic

• H01L45/1683

  Electricity · mapped topic

• H01L45/1246

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic