Formation of a thermopile sensor utilizing CMOS fabrication techniques

Patent metadata

Field	Value
Publication number	US-9412927-B2
Application number	US-201414573156-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	May 7, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Techniques are described to form an absorption stack proximate to a thermopile sensor. In one or more implementations, a thermopile sensor is formed proximate to a semiconductor wafer. An absorption stack is formed proximate to the semiconductor wafer and includes a first layer, a second layer, and a third layer. The first layer may be a material having absorption and/or reflective characteristics. The second layer may be a material having wave phase shift characteristic characteristics. The third layer may be a material having a reflective characteristic.

First claim

What is claimed is:

1. A process comprising:
forming a thermopile sensor proximate to a semiconductor wafer, the thermopile sensor comprising at least a first thermocouple material and a second thermocouple material; and
forming an absorption stack proximate to the semiconductor wafer, the absorption stack comprising a first planar layer having at least one of an absorption characteristic or a reflective characteristic, a second planar layer having a wave phase shift characteristic, the second planar layer different from the first planar layer, and a third planar layer having a reflective characteristic, the third planar layer different from the first planar layer and the second planar layer, the first planar layer, the second planar layer, and the third planar layer arranged in a stacked configuration, wherein the absorption stack is horizontally offset with respect to the thermopile sensor.

2. The process as recited in claim 1 , wherein the first planar layer comprises a titanium material, the second planar layer comprises at least one of a polysilicon material, an amorphous silicon material, or a germanium material, and the third planar layer comprises aluminum.

3. The process as recited in claim 1 , wherein an oxide layer is disposed over the third planar layer.

4. The process as recited in claim 1 , wherein the first planar layer has a thickness ranging from about three nanometers to about five nanometers, the second planar layer has a thickness ranging from about six hundred nanometers to about seven hundred and fifty nanometers, and the third planar layer has a thickness ranging from about twenty nanometers to about fifty nanometers.

5. The process as recited in claim 1 , forming a first passivation layer over the thermopile sensor.

6. The process as recited in claim 5 , wherein the first passivation layer comprises a phosphosilicate glass (PSG) material.

7. The process as recited in claim 5 , wherein a thickness of the first passivation layer ranges from about fifty nanometers to about one hundred nanometers.

8. The process as recited in claim 5 , further comprising forming a second passivation layer and a third passivation layer over the absorption stack.

9. The process as recited in claim 8 , wherein the second passivation layer comprises a silicon-nitride material, and the third passivation layer comprises a borophosphosilicate glass material.

10. A semiconductor device comprising:
a semiconductor substrate;
a thermopile sensor disposed proximate the semiconductor substrate, the thermopile sensor comprising at least a first thermocouple material and a second thermocouple material;
an absorption stack disposed proximate to the semiconductor substrate, the absorption stack comprising a first planar layer having at least one of an absorption characteristic or a reflective characteristic, a second planar layer having a wave phase shift characteristic, the second planar layer different from the first planar layer, and a third layer having a reflective characteristic, the third planar layer different from the first planar layer and the second planar layer, the first planar layer, the second planar layer, and the third planar layer arranged in a stacked configuration, wherein the absorption stack is horizontally offset with respect to the thermopile sensor; and
at least one passivation layer disposed proximate to the semiconductor wafer, the at least one passivation layer disposed over the absorption stack.

11. The semiconductor device as recited in claim 10 , wherein the first planar layer comprises a titanium material, the second planar layer comprises at least one of a polysilicon material, an amorphous silicon material, or a germanium material, and the third planar layer comprises aluminum.

12. The semiconductor device as recited in claim 10 , further comprising an oxide layer is disposed over the third planar layer.

13. The semiconductor device as recited in claim 10 , wherein the first planar layer has a thickness ranging from about three nanometers to about five nanometers, the second planar layer has a thickness ranging from about six hundred nanometers to about seven hundred and fifty nanometers, and the third planar layer has a thickness ranging from about twenty nanometers to about fifty nanometers.

14. The semiconductor device as recited in claim 10 , wherein the at least one passivation layer comprises a first passivation layer and a second passivation layer.

15. The semiconductor device as recited in claim 14 , wherein the first passivation layer comprises a silicon-nitride material, and the second passivation layer comprises a borophosphosilicate glass material.

16. The semiconductor device as recited in claim 15 , wherein the first passivation layer and the second passivation layer increases an absorption characteristic of the absorption stack.

17. A semiconductor device comprising:
a semiconductor substrate;
a thermopile sensor disposed proximate the semiconductor substrate, the thermopile sensor comprising at least a first thermocouple material and a second thermocouple material;
an absorption stack disposed proximate to the semiconductor substrate, the absorption stack comprising a first planar layer having at least one of an absorption characteristic or a reflective characteristic, a second planar layer having a wave phase shift characteristic, the second planar layer different from the first planar layer, and a third planar layer having a reflective characteristic, the third planar layer different from the first planar layer and the second planar layer, the first planar layer, the second planar layer, and the third planar layer arranged in a stacked configuration, wherein the absorption stack is horizontally offset with respect to the thermopile sensor;
a first passivation layer disposed proximate to the semiconductor wafer, the first passivation layer disposed over the absorption stack;
a second passivation layer disposed proximate to the semiconductor wafer, the second passivation layer disposed over the first passivation layer; and
a third passivation layer disposed proximate to the semiconductor wafer, at least a portion of the third passivation layer disposed over the thermopile sensor and the absorption stack is formed directly over the third passivation layer, wherein the first passivation layer and the second passivation layer are disposed over the third passivation layer.

18. The semiconductor device as recited in claim 17 , wherein the first planar layer comprises a titanium material, the second planar layer comprises at least one of a polysilicon material, an amorphous silicon material, or a germanium material, and the third planar layer comprises aluminum.

19. The semiconductor device as recited in claim 17 , wherein the first passivation layer comprises a silicon-nitride material, and the second passivation layer comprises a borophosphosilicate glass material.

Assignees

• Maxim Integrated Products

Inventors

• Emadi Arvin
• Barnett Stanley

Classifications

• H10F39/184

  Infrared image sensors · CPC title

• H01L35/04

  Electricity · mapped topic

• H01L35/14

  Electricity · mapped topic

• H01L35/00 Primary

  Electricity · mapped topic

• H01L35/34

  Electricity · mapped topic