Methods and apparatus for MOS capacitors in replacement gate process

Patent metadata

Field	Value
Publication number	US-9412883-B2
Application number	US-201113303083-A
Country	US
Kind code	B2
Filing date	Nov 22, 2011
Priority date	Nov 22, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
an isolation region in a semiconductor substrate defining a first region and a second region of the substrate;
a high-k metal gate device formed in the first region proximal to the isolation region, the high-k metal gate device comprising a high-k gate dielectric and a metal gate;
a first polysilicon gate MOS capacitor and a second polysilicon gate MOS capacitor formed in the second region proximal to the isolation region, each of the first polysilicon gate MOS capacitor and the second polysilicon gate MOS capacitor comprising a gate dielectric and a polysilicon gate, the gate dielectric and the high-k gate dielectric having different material compositions, wherein a first edge of the first polysilicon gate MOS capacitor is spaced apart from a corresponding second edge of the second polysilicon gate MOS capacitor by a minimum pitch, and wherein the minimum pitch is determined by processing limitations for forming metal gates in the apparatus; and
an interlayer dielectric layer over the substrate, wherein the interlayer dielectric layer contacts a sidewall of the first polysilicon gate MOS capacitor and a sidewall of the high-k metal gate device.

2. The apparatus of claim 1 , wherein:
the gate dielectric of the first polysilicon gate MOS capacitor is formed over and in direct contact with the substrate, the gate dielectric forming a capacitor dielectric; and
the polysilicon gate is formed over the gate dielectric and forms a top plate of the first polysilicon gate MOS capacitor, wherein a bottommost surface of the polysilicon gate is above a top surface of the substrate.

3. The apparatus of claim 2 wherein the gate dielectric comprises silicon oxynitride.

4. The apparatus of claim 2 wherein the polysilicon gate is doped to form a polysilicon resistor.

5. The apparatus of claim 1 , wherein the high-k metal gate device further comprises:
the high-k gate dielectric disposed over the substrate; and
the metal gate disposed over the high-k gate dielectric, the metal gate consisting substantially of a metal or metal composition.

6. The apparatus of claim 5 , wherein the high-k gate dielectric comprises hafnium.

7. The apparatus of claim 6 , wherein the metal containing gate comprises titanium.

8. An apparatus, comprising:
a plurality of polysilicon gate strips disposed over a semiconductor substrate forming top plates of MOS capacitors, in parallel and spaced apart by at least a minimum pitch distance, wherein the minimum pitch distance is a distance between corresponding edges of two adjacent polysilicon gate strips, and wherein the minimum pitch is determined by processing limitations for forming metal gates in the apparatus;
an interlayer dielectric layer over the semiconductor substrate, wherein the interlayer dielectric layer contacts at least one sidewall of each of the plurality of polysilicon gate strips;
gate dielectric material disposed under each of the polysilicon gate strips forming a capacitor dielectric for the MOS capacitors;
at least one high-k metal gate device the high-k metal gate device comprising a high-k gate dielectric and a metal gate disposed on the semiconductor substrate proximal to the plurality of polysilicon gate strips, the at least one high-k metal gate device having a source/drain region; and
a portion of the semiconductor substrate underlying the polysilicon gate strips doped to form a bottom plate for the MOS capacitors, the bottom plate for the MOS capacitors being electrically connected to the at least one high-k metal gate device through the source/drain region.

9. The apparatus of claim 8 , wherein the gate dielectric material comprises silicon oxynitride.

10. The apparatus of claim 8 , wherein the polysilicon gate strips are doped to form polysilicon resistor material.

11. The apparatus of claim 8 , wherein the top plates of the MOS capacitors are coupled together to form a parallel capacitor.

12. The apparatus of claim 8 , wherein the high-k gate dielectrio that comprises hafnium.

13. The apparatus of claim 8 , wherein the high-k gate dielectric comprises one selected from the group consisting essentially of hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide.

14. The apparatus of claim 12 and further comprising an isolation region formed on the semiconductor substrate between the high-k metal gate device and the plurality of polysilicon gate strips.

15. An apparatus comprising:
a semiconductor substrate, the semiconductor substrate having a first region and a second region separated by an isolation region;
a doped region formed in the first region of the semiconductor substrate, wherein the doped region forms a bottom capacitor plate;
a gate dielectric layer formed over the doped region, the gate dielectric layer comprising at least one gate dielectric feature;
a gate polysilicon layer formed over the gate dielectric layer, the gate polysilicon layer comprising a plurality of parallel polysilicon gates over the at least one gate dielectric feature, wherein the plurality of parallel polysilicon gates form a top capacitor plate, wherein corresponding edges of adjacent polysilicon gates are spaced apart from each other by a first distance, and wherein the first distance is a minimum pitch for forming metal gates for a technology node by which the apparatus is manufactured;
a high-k dielectric layer formed over the second region of the substrate;
a high-k metal gate formed over the high-k dielectric layer, a topmost surface of a metal containing portion of the high-k metal gate being coplanar with a topmost surface of a polysilicon portion of each of the plurality of parallel polysilicon gates; and
an interlayer dielectric layer over the semiconductor substrate, the interlayer dielectric layer being a continuous layer extending from the high-k metal gate to the plurality of parallel polysilicon gates.

16. The apparatus of claim 15 , further comprising a conductive feature overlying and electrically connecting the plurality of parallel polysilicon gates.

17. The apparatus of claim 15 , wherein the isolation region is a shallow trench isolation (STI) feature formed in the semiconductor substrate.

18. The apparatus of claim 16 , wherein a conductive feature comprises vias contacting the plurality of parallel polysilicon gates and an overlying common connector contacting the vias.

19. The apparatus of claim 15 , wherein the top capacitor plate and the high-k metal gate are in a plane above a top surface of the isolation region.

20. The apparatus of claim 18 , wherein the overlying common connector does not overlie the high-k metal gate.

21. The apparatus of claim 15 , wherein the plurality of parallel polysilicon gates are connected by the doped region.

Assignees

• Wang Pai-Chieh
• Hsieh Tung-Heng
• Huang Yimin
• Chen Chung-Hui
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Pai-Chieh
• Hsieh Tung-Heng
• Huang Yimin
• Chen Chung-Hui

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/217

  of only conductor-insulator-semiconductor capacitors · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title