Dual gate structure

Patent metadata

Field	Value
Publication number	US-9412845-B2
Application number	US-201414519068-A
Country	US
Kind code	B2
Filing date	Oct 20, 2014
Priority date	Oct 20, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.

First claim

What is claimed is:

1. A method for forming a dual gate structure for a vertical TFT, comprising:
forming one or more layers of polysilicon;
etching a plurality of trenches extending through the one or more layers of polysilicon;
forming a plurality of oxide pillars by filling the plurality of trenches with an insulating material;
performing a first etching process, the first etching process includes etching a first set of oxide pillars of the plurality of oxide pillars to a first initial depth, the plurality of oxide pillars includes a second set of oxide pillars different from the first set of oxide pillars;
performing a second etching process subsequent to the performing the first etching process, the second etching process forms a first set of trenches by etching the first set of oxide pillars from the first initial depth to a first depth and forms a second set of trenches by etching the second set of oxide pillars to a second depth higher than the first depth;
forming a plurality of gate dielectrics within the first set of trenches and the second set of trenches; and
forming a first set of gate structures and a second set of gate structures, the forming the first set of gate structures and the second set of gate structures includes filling the first set of trenches and the second set of trenches with a gate material subsequent to the forming the plurality of gate dielectrics.

2. The method of claim 1 , further comprising:
performing a third etching process, the third etching process includes etching the first set of gate structures to a second initial depth;
performing a fourth etching process subsequent to the performing the third etching process, the fourth etching process forms a third set of trenches by etching the first set of gate structures from the second initial depth to a third depth and forms a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth; and
filling the third set of trenches and the fourth set of trenches with the insulating material.

3. The method of claim 2 , wherein:
the third depth is lower than the second initial depth, the fourth depth is higher than the second initial depth.

4. The method of claim 2 , wherein:
the forming a plurality of gate dielectrics includes conformally depositing a gate dielectric material within the first set of trenches and the second set of trenches.

5. The method of claim 4 , wherein:
the third etching process removes the gate material while being highly selective to the gate dielectric material.

6. The method of claim 4 , wherein:
the gate material comprises at least one of titanium nitride or n+ polysilicon; and
the gate dielectric material comprises at least one of silicon oxide or a high-k dielectric material.

7. The method of claim 1 , wherein:
the first depth and the second depth are both lower than the first initial depth.

8. The method of claim 1 , wherein:
the insulating material comprises silicon dioxide.

9. The method of claim 1 , wherein:
the one or more layers of polysilicon include a first n-type polysilicon layer, a second p-type polysilicon layer formed over the first n-type polysilicon layer, a third n-type polysilicon layer formed over the second p-type polysilicon layer, a fourth p-type polysilicon layer formed over the third n-type polysilicon layer, and a fifth n-type polysilicon layer formed over the fourth p-type polysilicon layer.

10. The method of claim 9 , wherein:
the second p-type polysilicon layer is associated with a first transistor channel of the vertical TFT and the fourth p-type polysilicon layer is associated with a second transistor channel of the vertical TFT, the vertical TFT may be placed into a conducting state when both the first transistor channel and the second transistor channel are inverted.

11. The method of claim 1 wherein:
the forming one or more layers of polysilicon includes forming the one or more layers of polysilicon above one or more global bit lines associated with a three-dimensional memory array.

12. The method of claim 1 , wherein:
the first etching process comprises a first timed etch; and
the second etching process comprises a second timed etch that is performed subsequent to the first timed etch, the second timed etch etches the first set of oxide pillars from the first initial depth to the first depth while the second set of oxide pillars is etched to the second depth higher than the first depth.

13. A method for forming a dual gate structure for a vertical TFT, comprising:
forming one or more polysilicon layers;
forming a plurality of oxide pillars, the forming a plurality of oxide pillars includes etching a plurality of trenches extending through the one or more polysilicon layers and filling the plurality of trenches with an insulating material, the plurality of oxide pillars includes a first set of oxide pillars and a second set of oxide pillars different from the first set of oxide pillars;
forming a first set of trenches by etching the first set of oxide pillars to a first depth at the same time as forming a second set of trenches by etching the second set of oxide pillars to a second depth higher than the first depth;
forming a plurality of gate dielectrics within the first set of trenches and the second set of trenches;
forming a first set of gate structures and a second set of gate structures, the forming the first set of gate structures and the second set of gate structures includes filling the first set of trenches and the second set of trenches with a gate material subsequent to the forming the plurality of gate dielectrics;
forming a third set of trenches by etching the first set of gate structures to a third depth;
forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth; and
filling the third set of trenches and the fourth set of trenches with the insulating material.

14. The method of claim 13 , wherein:
the forming a plurality of gate dielectrics includes depositing a gate dielectric material within the first set of trenches and the second set of trenches.

15. The method of claim 14 , wherein:
the third etching process removes the gate material while being highly selective to the gate dielectric material.

16. The method of claim 13 , wherein:
the one or more polysilicon layers include a first n-type polysilicon layer, a second p-type polysilicon layer formed over the first n-type polysilicon layer, a third n-type polysilicon layer formed over the second p-type polysilicon layer, a fourth p-type polysilicon layer formed over the third n-type polysilicon layer, and a fifth n-type polysilicon layer formed over the fourth p-type polysilicon layer.

17. The method of claim 16 , wherein:
the second p-type polysilicon layer is associated with a first transistor channel of the vertical TFT and the fourth p-type polysilicon layer is associated with a second transistor channel of the vertical TFT, the vertical TFT may be placed into a conducting state when both the first transistor channel and the second transistor channel are inverted.

18. The method of claim 13 , wherein:
the forming one or more polysilicon layers includes forming the one or more polysilicon layers above one or more global bit lines associated with a three-dimensional memory array.

19. A method for manufacturing a semiconductor memory, comprising:
forming one or more vertical TFTs, the forming one or more vertical TFTs includes performing a first etching proc

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Wu Wei-Te
• Wu Ming-Che
• Chen Yung-Tin

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/0195

  the components including vertical IGFETs · CPC title