Semiconductor device and method of manufacturing the same

US9412823B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9412823-B2
Application numberUS-201514855669-A
CountryUS
Kind codeB2
Filing dateSep 16, 2015
Priority dateMar 22, 2013
Publication dateAug 9, 2016
Grant dateAug 9, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×10 18 cm −3 and not higher than 1×10 22 cm −3 , an SiC layer formed on the first face, a first electrode formed on the first face side, and a second electrode formed on the second face.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a p-type SiC substrate having a first face and a second face, the p-type SiC substrate containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being at least one of a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and a combination of B (boron) and P (phosphorus), a ratio of a concentration of the element D to a concentration of the element A forming at least one of the combinations being higher than 0.33 but lower than 0.995, the concentration of the element A forming at least one of the combinations being not lower than 1×10 18 cm −3 and not higher than 1×10 22 cm −3 ; an SiC layer formed on the first face; a first electrode formed on a first face side; and a second electrode formed on the second face. 2. The device according to claim 1 , wherein the ratio of the concentration of the element D to the concentration of the element A is higher than 0.40 but lower than 0.95. 3. The device according to claim 1 , wherein the concentration of the element A is 1×10 19 cm −3 or higher. 4. The device according to claim 1 , wherein an acceptor level of the element A is 150 meV or less. 5. The device according to claim 1 , wherein 90% or more of the element D is in a lattice site location nearest to the element A.

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What does patent US9412823B2 cover?
A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and …
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10P14/3408. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).