Semiconductor device including multiple nanowire transistor

Patent metadata

Field	Value
Publication number	US-9412816-B2
Application number	US-201514605041-A
Country	US
Kind code	B2
Filing date	Jan 26, 2015
Priority date	Feb 21, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A semiconductor device comprises at least two nanowire patterns over a substrate, wherein the at least two nanowire patterns have increasingly narrower widths as they extend away from the substrate and have different channel impurity concentrations. A gate electrode surrounds at least a part of the at least two nanowire patterns. A gate dielectric film is disposed between the at least two nanowire patterns and the gate electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate extending in a longitudinal direction;
at least two nanowire patterns over the substrate;
a gate electrode surrounding at least a part of the at least two nanowire patterns; and
a gate dielectric film between the at least two nanowire patterns and the gate electrode in a direction substantially perpendicular to the longitudinal direction, wherein longitudinal widths of the at least two nanowire patterns become narrower in a direction away from the substrate and have different channel impurity concentrations;
wherein the at least two nanowire patterns include:
a first nanowire pattern having a first channel region at a first distance from the substrate and having a first channel impurity concentration and a first channel width, and
a second nanowire pattern having a second channel region at a second distance from the substrate greater than the first distance, having a second channel impurity concentration higher than the first channel impurity concentration, and having a second channel width smaller than the first channel width; and
wherein the at least two nanowire patterns further include a third nanowire pattern having a third channel region at a third distance from the substrate greater than the second distance, having a third channel impurity concentration higher than the second channel impurity concentration, and a third channel width smaller than the second channel width, wherein the first channel threshold voltage of the first channel region is substantially the same as the third channel threshold voltage of the third channel region.

2. The semiconductor device of claim 1 , wherein the at least two nanowire patterns include respective channel regions that have higher channel impurity concentrations in the direction away from the substrate and have different channel widths.

3. The semiconductor device of claim 2 , wherein the respective channel regions have a substantially same channel threshold voltage.

4. The semiconductor device of claim 2 , further comprising:
a pair of source/drain regions connected to respective end portions of the respective channel regions of the at least two nanowire patterns, and spaced apart from the substrate by a distance.

5. The semiconductor device of claim 1 , wherein the at least two nanowire patterns include one nanowire pattern closest to the substrate, wherein the one nanowire pattern comprises an undoped semiconductor material.

6. The semiconductor device of claim 1 , wherein the first channel threshold voltage of the first channel region is substantially the same as the second channel threshold voltage of the second channel region.

7. The semiconductor device of claim 1 , wherein the at least two nanowire patterns have substantially a same thickness.

8. The semiconductor device of claim 1 , further comprising:
a plurality of sacrificial film patterns between nanowire patterns of the at least two nanowire patterns, respectively, wherein the gate electrode passes through at least a part of each sacrificial film pattern.

9. The semiconductor device of claim 1 , wherein the at least two nanowire patterns are at different distances from the substrate such that at least a part of the respective nanowire patterns overlap in a direction perpendicular with respect to a surface of the substrate.

10. The semiconductor device of claim 1 , further comprising:
a device isolation film, wherein the at least two nanowire patterns are part of a fin shaped pattern structure that upwardly protrudes from a top surface of the device isolation film.

11. A semiconductor device, comprising:
a plurality of nanowire patterns over a substrate extending in a longitudinal direction, wherein longitudinal widths and transversal widths of the plurality of nanowire patterns become narrower in a direction away from the substrate, the plurality of nanowire patterns having a plurality of channels, the plurality of channels having a decreasing longitudinal channel width in a direction away from the substrate;
a gate electrode around one or more of the plurality of nanowire patterns;
a gate dielectric film between the gate electrode and one or more of the plurality of nanowire patterns in a direction substantially perpendicular to the longitudinal direction.

12. The semiconductor device of claim 11 , wherein:
a channel threshold voltage of one or more of the channels increases in a direction away from the substrate.

13. The semiconductor device of claim 11 , wherein the gate electrode comprises a plurality of sub-gate electrodes, each of the sub-gate electrodes being between two adjacent channels.

14. The semiconductor device of claim 11 , wherein a width of one or more of the plurality of nanowire patterns decreases in the direction away from the substrate.

15. The semiconductor device of claim 11 , further comprising:
one or more sacrificial film patterns between two adjacent nanowire patterns of the plurality of nanowire patterns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Jung-Gil
• Kim Sang-Su
• Kwon Tae-Yong

Classifications

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title