Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates with etch back process
US-2024072145-A1 · Feb 29, 2024 · US
US9412815B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9412815-B2 |
| Application number | US-201414496048-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 25, 2014 |
| Priority date | Mar 28, 2013 |
| Publication date | Aug 9, 2016 |
| Grant date | Aug 9, 2016 |
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A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a substrate having at least one electrically insulating portion; a first graphene electrode formed on a surface defined by a location area of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode; and a second graphene electrode formed on the surface of the substrate such that the electrically insulating portion is interposed between the bulk portion of the substrate and the second graphene electrode, the second graphene electrode disposed opposite the first graphene electrode to define an exposed substrate area therebetween, wherein the first graphene electrode is configured to receive a voltage source and the second graphene electrode is configured to receive a ground source, the voltage and ground sources inducing an electric field including a plurality of field lines, the electric field forcing the at least one carbon nanotube to the exposed substrate area and aligning the at least one carbon nanotube in a direction parallel to the field lines, and wherein the first and second graphene electrodes each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, each teeth-like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first peak of a respective first teeth-like portion and a second end of each carbon nanotube contacts a second peak of a respective second teeth-like portion. 2. The semiconductor device of claim 1 , further comprising at least one carbon nanotube deposited on the surface of the substrate. 3. The semiconductor device of claim 2 , wherein the substrate is formed from an electrically insulating material. 4. The semiconductor device of claim 3 , wherein the insulating portion is integrally formed with the substrate and formed from the same material as the substrate. 5. A semiconductor device, comprising: a substrate wafer configured to insulate electrical current from flowing therethrough; a graphene electrode network including first and second electrode branches separated from one another by an exposed portion of the substrate wafer, the first and second electrode branches extending along the substrate in direction parallel to one another, the first electrode branch configured to receive a voltage source and the second electrode branch configured to receive a ground source; and a plurality of carbon nanotube arrays arranged between the first and second electrode branches, the plurality of carbon nanotube arrays including a plurality of carbon nanotubes aligned perpendicular to the first and second electrode branches in response to an electric field induced by applying the voltage and ground sources, wherein the first and second graphene electrode branches each include a plurality of teeth-like portions arranged in sequence to form a saw-tooth edge defining a pitch, each teeth-like portion separated from another by the pitch and including a base having a length and a peak that extends into the location area such that the length of the base substantially matches the pitch, wherein each carbon nanotube included in a respective carbon nanotube array is aligned between a first teeth-like portion of the first graphene terminal and a second teeth-like portion of the second graphene terminal such that a first end of each carbon nanotube contacts a first peak of a respective first teeth-like portion and a second end of each carbon nanotube contacts a second peak of a respective second teeth-like portion. 6. The semiconductor device of claim 5 , wherein the first and second electrode branches extend in a plurality of different directions such that the plurality of carbon nanotube arrays are aligned differently according to the directions of the first and second electrode branches. 7. The semiconductor device of claim 6 , wherein the first electrode branch includes at least one first graphene electrode and the second electrode branch includes at least one second graphene electrode disposed directly opposite from the first graphene electrode.
Carbon, e.g. diamond-like carbon · CPC title
oriented parallel to substrates · CPC title
Nanosized electrodes, e.g. nanowire electrodes · CPC title
Electrodes ohmically coupled to a semiconductor · CPC title
Graphene · CPC title
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