Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

Patent metadata

Field	Value
Publication number	US-9412705-B2
Application number	US-201114128011-A
Country	US
Kind code	B2
Filing date	Jun 27, 2011
Priority date	Jun 27, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A ferroelectric memory cell ( 1 ) and a memory device ( 100 ) comprising one or more such cells ( 1 ). The ferroelectric memory cell comprises a stack ( 4 ) of layers arranged on a flexible substrate ( 3 ). Said stack comprises an electrically active part ( 4 a ) and a protective layer ( 11 ) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer ( 5 ) and a top electrode layer ( 9 ) and at least one ferroelectric memory material layer ( 7 ) between said electrodes. The stack further comprises a buffer layer ( 13 ) arranged between the top electrode layer ( 9 ) and the protective layer ( 11 ). The buffer layer ( 13 ) is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer ( 11 ) and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part ( 4 a ), thereby reducing the risk of short circuit to occur between the electrodes.

First claim

The invention claimed is:

1. A ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate, wherein said stack comprises an electrically active part and a protective layer for protecting the electrically active part against scratches and abrasion, wherein said electrically active part comprises a bottom electrode layer and a top electrode layer and at least one ferroelectric memory material layer between said electrodes, wherein the stack further comprises a buffer layer, arranged between the top electrode layer and the protective layer, the buffer layer being adapted for at least partially absorbing a lateral dimensional change occurring in the protective layer and thus preventing said dimensional change from being transferred to the electrically active part, wherein the buffer layer is adapted for at least partially absorbing the lateral dimensional change by being of a coherent material and having such layer thickness that a lateral dimensional deformation in a top portion of the buffer layer facing the protective layer results in substantially less lateral dimensional deformation in a bottom portion facing the electrically active part, when said lateral dimensional deformation in the upper part is caused by the lateral dimensional change of the protective layer, the difference in lateral deformation between the top and bottom portions corresponding to absorbed lateral dimensional change.

2. The ferroelectric memory cell as claimed in claim 1 , wherein at least partially absorbing the lateral dimensional change comprises absorbing the lateral dimensional change by at least 30%.

3. The ferroelectric memory cell as claimed in claim 1 , wherein the buffer layer comprises a material with a glass transition temperature that is lower than 30 degrees C.

4. The ferroelectric memory cell as claimed in claim 3 , wherein the material is a hybrid material comprising at least one material component that has a glass transition temperature that is lower than 30 degrees C.

5. The ferroelectric memory cell as claimed in claim 1 , wherein the buffer layer comprises a material or mix of two or more materials from any one of the following:
silicon rubber, natural rubber, polypropylene glycol, polyvinyl acetate and acrylate based resins.

6. The ferroelectric memory cell as claimed in claim 1 , wherein the ferroelectric memory material layer comprises an organic, preferably polymeric, ferroelectric memory material.

7. The ferroelectric memory cell as claimed in claim 1 , wherein said lateral dimensional change of the protective layer is such causable by hardening of the protective layer, such as by curing, or by temperature differences in an operational temperature range of the ferroelectric memory cell, such as −10C to +50C.

8. The ferroelectric memory cell as claimed in claim 1 , wherein the electrically active part and/or the buffer layer has been printed on the flexible substrate.

9. The ferroelectric memory cell as claimed in claim 1 , wherein the protective layer is directly attached to the buffer layer.

10. The ferroelectric memory cell as claimed in claim 1 , wherein the protective layer comprises a protective film and an adhesive attaching the protective film to the buffer layer, the material that has been hardened being the adhesive.

11. The ferroelectric memory cell as claimed in claim 1 , wherein the protective layer is a protective film and the buffer layer forms an adhesive attaching the protective film to the rest of the stack.

12. The ferroelectric memory cell as claimed in claim 1 , wherein the top electrode layer comprises a top surface which faces the protective layer, and wherein the buffer layer extends along the entire top surface of the top electrode layer in the ferroelectric memory cell.

13. A memory device comprising one or more memory cells as claimed in claim 1 , preferably a passive matrix memory device.

Assignees

• Karlsson Christer
• Hagel Olle Jonny
• Nilsson Jakob
• Bröms Per
• Thin Film Electronics Asa

Inventors

• Karlsson Christer
• Hagel Olle Jonny
• Nilsson Jakob
• Bröms Per

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• G11C11/22

  using ferroelectric elements · CPC title

• G11B9/02 Primary

  using ferroelectric record carriers; Record carriers therefor · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title