Semiconductor device having jumper pattern and blocking pattern

Patent metadata

Field	Value
Publication number	US-9412693-B2
Application number	US-201414174705-A
Country	US
Kind code	B2
Filing date	Feb 6, 2014
Priority date	May 10, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a gate structure disposed above the substrate;
a first interlayer insulating layer disposed above the substrate;
a blocking pattern disposed above the first interlayer insulating layer and the gate structure; and
a jumper pattern disposed above the blocking pattern, the jumper pattern including jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate at first and second sides of the gate structure, and a jumper section electrically connecting the jumper contact plugs,
wherein:
the blocking pattern is disposed horizontally between the jumper contact plugs, and
side surfaces of the blocking pattern are not vertically aligned with side surfaces of the jumper contact plugs.

2. The semiconductor device of claim 1 , wherein the blocking pattern vertically overlaps the gate structure.

3. The semiconductor device of claim 1 , wherein the blocking pattern comprises a conductive material.

4. The semiconductor device of claim 1 , wherein an upper surface of the blocking pattern is in contact with a bottom surface of the jumper section.

5. The semiconductor device of claim 4 , wherein the side surfaces of the jumper contact plugs and the jumper section are in contact with the side surfaces of the blocking pattern.

6. The semiconductor device of claim 1 , further comprising:
a stopper layer including silicon nitride formed above the first interlayer insulating layer;
a second interlayer insulating layer formed above the first interlayer insulating layer and surrounding at least some of the jumper section; and
an upper insulating layer formed above the second interlayer insulating layer and the jumper section.

7. The semiconductor device of claim 6 , wherein the blocking pattern is in contact with the stopper layer.

8. The semiconductor device of claim 1 , further comprising a resistor pattern formed above the first interlayer insulating layer.

9. The semiconductor device of claim 8 , further comprising a resistor contact plug in contact with the resistor pattern, wherein an upper surface of the resistor contact plug and an upper surface of the jumper section are coplanar.

10. The semiconductor device of claim 8 , further comprising a fuse formed above the first interlayer insulating layer, wherein a lower surface of the fuse and a lower surface of the blocking pattern are coplanar.

11. The semiconductor device of claim 10 , further comprising a fuse contact plug in contact with the fuse, wherein an upper surface of the fuse contact plug and an upper surface of the jumper section are coplanar.

12. The semiconductor device of claim 1 , further comprising:
a capacitor lower electrode formed above the substrate and having substantially the same structure as the transistor gate structure;
a capping layer disposed on the capacitor lower electrode; and
a capacitor upper electrode formed above the first interlayer insulating layer, and
wherein the blocking pattern and the capacitor upper electrode comprise the same material.

13. The semiconductor device of claim 1 , wherein each of the jumper contact plugs includes a contact barrier layer and a contact core layer, and the contact barrier layer is in contact with the substrate, and surrounds a bottom and sides of the contact core layer, and the jumper section includes a jumper barrier layer and a jumper core layer, and the jumper barrier layer is in contact with an upper surface of the blocking pattern, and surrounds a bottom and sides of the jumper core layer.

14. The semiconductor device of claim 13 , wherein the contact barrier layer and the jumper barrier layer are formed from the same material.

15. A semiconductor device comprising:
a substrate;
a gate structure disposed above the substrate;
a first layer disposed above the substrate, the first layer formed using an insulating material and having a substantially planar top surface;
a second layer in contact with the top surface of the first layer, the second layer formed using a metal and including discrete first and second regions having substantially coplanar top surfaces;
a jumper pattern disposed on the top surface of the first region of the second layer, the jumper pattern including jumper contact plugs extending through the first layer to contact the substrate at first and second sides of the gate structure, and a jumper section electrically connecting the jumper contact plugs; and
a circuit component formed using the second region of the second layer, the circuit component being a resistor, a capacitor or a fuse,
wherein the jumper section and the jumper contact plugs are formed together as a continuous material.

16. The semiconductor device of claim 15 , wherein the circuit component is a capacitor having an electrode formed using the second region of the second layer.

17. The semiconductor device of claim 15 , wherein the circuit component is a resistor formed using the second region of the second layer, and further comprising a resistor contact plug connected to the top surface of the second region, the resistor contact plug having a top surface that is substantially coplanar with a top surface of the jumper pattern.

18. The semiconductor device of claim 15 , wherein the jumper pattern includes a barrier layer in contact with the first region of the second layer.

19. The semiconductor device of claim 15 , wherein the first layer comprises a stopper layer.

20. A semiconductor device comprising:
a substrate;
a gate structure disposed above the substrate;
a first interlayer insulating layer disposed above the substrate;
a blocking pattern disposed above the first interlayer insulating layer and the gate structure; and
a jumper pattern disposed above the blocking pattern, the jumper pattern including jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate at first and second sides of the gate structure, and a jumper section electrically connecting the jumper contact plugs,
wherein:
an upper surface of the blocking pattern is in contact with a bottom surface of the jumper section, and
side surfaces of the jumper contact plugs are in contact with side surfaces of the blocking pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yoon-Hae
• Yoon Jong-Shik
• Rhee Hwa-Sung

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title