Method of reading data from a nonvolatile memory device, nonvolatile memory device, and method of operating a memory system

Patent metadata

Field	Value
Publication number	US-9412471-B2
Application number	US-201414186504-A
Country	US
Kind code	B2
Filing date	Feb 21, 2014
Priority date	Mar 15, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

In a method of reading data from a nonvolatile memory device, a first read operation for memory cells coupled to a first word line is performed by applying a first read voltage to the first word line, a first read retry is performed to obtain an optimal read level regardless or independent of whether data read by the first read operation is error-correctable, and the optimal read level is stored to perform a subsequent second read operation using the optimal read level. Related methods and devices are also discussed.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device, the method comprising:
performing a read operation to read data from a memory cell of the memory device by applying a first read voltage to a first word line coupled thereto, wherein the memory cell corresponds to a first page of a memory block;
performing a read retry operation to read the data from the memory cell responsive to performing the read operation and independent of whether the data read in the read operation is correctable by an error correction code;
determining an error-correctable read voltage different from the first read voltage responsive to the read retry operation; and
performing a subsequent read operation to read data from a memory cell corresponding to a second page of the memory block by applying the error-correctable read voltage to a second word line coupled thereto.

2. The method of claim 1 , further comprising:
determining that the data read in the read operation is correctable by the error correction code;
wherein the read retry operation is performed responsive to determining that the data is correctable by the error correction code.

3. The method of claim 1 , wherein a probability that the data read in the subsequent read operation is correctable by the error correction code is increased responsive to performing the read retry operation.

4. The method of claim 1 , further comprising:
selectively performing or omitting a subsequent read retry operation for the second page dependent on whether the data read in the subsequent read operation is correctable by the error correction code,
wherein a read retry voltage of the subsequent read retry operation is based on a relationship between the first read retry voltage and the error-correctable read voltage.

5. The method of claim 1 , wherein the read operation is a soft decision read operation indicating a reliability of the data read in a preceding read operation, and wherein the subsequent read operation is a hard decision read operation indicating either a first or second state of the memory cell corresponding to the second page.

6. The method of claim 1 , wherein the read operation comprises a sequential read operation that is indicative of a sequence of the first page relative to a previously read page, and wherein the subsequent read operation comprises a random read operation that is independent of a sequence of the second page relative to the first page.

7. The method of claim 1 , wherein the read operation comprises an initial read operation after erasure of the memory block.

8. The method of claim 1 , wherein the error-correctable read voltage corresponds to the memory block, and further comprising:
storing respective error-correctable read voltages for each of a plurality of memory blocks.

9. The method of claim 1 , wherein the first and second word lines are coupled to respective memory cells that are remote from edges of the memory block.

10. The method of claim 1 , further comprising:
determining a number of program/erase operations previously performed on a memory block including the memory cell,
wherein the read retry operation is selectively performed based on the number of program/erase operations.

11. The method of claim 1 , wherein a number of read retry voltages applied to the first word line during the read retry operation and/or respective ranges therebetween vary based on whether the data read in the read operation is correctable by the error correction code.

12. A method of reading data from a nonvolatile memory device, the method comprising:
performing a first read operation for memory cells coupled to a first word line by applying a first read voltage to the first word line;
performing a first read retry to obtain an optimal read level regardless of whether data read by the first read operation are error-correctable; and
storing the optimal read level to perform a subsequent second read operation for memory cells coupled to a second word line using the optimal read level.

13. The method of claim 12 , further comprising:
performing the second read operation for the memory cells coupled to the second word line by applying a second read voltage having the optimal read level to the second word line; and
selectively performing a second read retry according to whether data read by the second read operation are error-correctable.

14. The method of claim 13 , further comprising:
determining whether the data read by the second read operation are error-correctable,
wherein selectively performing the second read retry comprises:
when the data read by the second read operation are determined to be error-correctable, completing the second read operation without performing the second read retry; and
when the data read by the second read operation are determined not to be error-correctable, performing the second read retry.

15. The method of claim 14 , wherein the second read retry is performed using a result of the first read retry.

16. The method of claim 15 , wherein, when the optimal read level lower than a voltage level of the first read voltage is obtained as the result of the first read retry, the second read retry is performed by applying read retry voltages having voltage levels lower than the voltage level of the first read voltage to the second word line, and
wherein, when the optimal read level higher than the voltage level of the first read voltage is obtained as the result of the first read retry, the second read retry is performed by applying read retry voltages having voltage levels higher than the voltage level of the first read voltage to the second word line.

17. The method of claim 12 , further comprising:
determining whether the data read by the first read operation are error-correctable,
wherein performing the first read retry comprises:
when the data read by the first read operation are determined not to be error-correctable, performing the first read retry using first read retry voltages having a first range; and
when the data read by the first read operation are determined to be error-correctable, performing the first read retry using second read retry voltages having a second range narrower than the first range.

18. The method of claim 17 , wherein a quantity of the second read retry voltages is less than a quantity of the first read retry voltages.

19. The method of claim 12 , further comprising:
performing an error correction on the data read by the first read operation using a Bose-Chaudhuri-Hocquenghem (BCH) code.

20. The method of claim 12 , further comprising:
performing an error correction on the data read by the first read operation using a low density parity check (LDPC) code.

21. The method of claim 12 , wherein performing the first read operation comprises:
performing a first hard decision read operation that reads first hard decision data from the memory cells coupled to the first word line by applying the first read voltage to the first word line;
determining whether the first hard decision data read by the first hard decision read operation are error-correctable; and
when the first hard decision data are determined not to be error-correctable, performing a first soft decision read operation that reads first soft decision data having reliability information for the first hard decision data from the memory cells coupled to the first word line.

22. The method of claim 21 , wherein, even when the first hard decision data are error-corr

Assignees

• Kim Kyung-Ryun
• Yoon Sang-Yong
• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Ryun
• Yoon Sang-Yong

Classifications

• G11C29/021

  in voltage or current generators · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title