Memory arrays

Patent metadata

Field	Value
Publication number	US-9412421-B2
Application number	US-201313937994-A
Country	US
Kind code	B2
Filing date	Jul 9, 2013
Priority date	Jun 7, 2010
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

First claim

I claim:

1. A memory array comprising a plurality of memory cell units; the array comprising multiple elevational levels of wordlines, and planes through each level; the areas of the individual memory cell units along the planes being less than 4F 2 relative to wordlines, bitlines, and spaces consumed by the memory cell units.

2. The memory array of claim 1 wherein the areas of the individual memory cell units along the planes are 2F 2 relative to wordlines, bitlines, and spaces consumed by the memory cell units.

3. The memory array of claim 1 wherein the memory cell units comprise phase change material, and are directly between wordlines and bitlines; and wherein the only material directly between the wordlines and bitlines is the phase change material.

4. The memory array of claim 1 comprising:
global bitlines extending along a first horizontal direction; the global bitlines comprising a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level; the global bitlines of the first series alternating with the global bitlines of the second series;
vertical local bitlines extending perpendicularly to the global bitlines;
wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction; the wordlines being stacked in a two-dimensional array comprising vertical columns and horizontal rows; the vertical columns of the wordline array comprising two or more wordlines; the vertical local bitlines extending through the wordline array so that vertical local bitlines are between adjacent vertical columns of the wordline array; and
memory cell material between the wordlines and the vertical local bitlines; the memory cell material forming memory cells of the memory cell units, with individual memory cells being uniquely addressed by wordline/global bitline combinations.

5. The memory array of claim 4 wherein the global bitlines of the first series are on an opposite side of the wordlines as the global bitlines of the second series.

6. The memory array of claim 4 wherein the global bitlines of the first series are on a common side of the wordlines as the global bitlines of the second series.

7. The memory array of claim 4 wherein the global bitlines of the first series are on an opposite side of the wordlines as the global bitlines of the second series; wherein the memory cell material is the only material directly between the wordlines and the vertical local bitlines; and wherein the memory cell material is chalcogenide-containing phase change material.

8. The memory array of claim 4 wherein the memory cell material comprises chalcogenide-containing phase change material.

9. The memory array of claim 4 wherein the memory cell material comprises alloys of germanium, antimony and tellurium.

10. A memory array comprising:
a plurality of memory cell units comprising access devices other than transistors; and
multiple elevational levels of wordlines, and planes through each level; the areas of the individual memory cell units along the planes being less than 4F 2 relative to wordlines, bitlines, access devices and spaces consumed by the memory cell units.

11. The memory array of claim 10 wherein the access devices comprise diodes.

12. The memory array of claim 10 wherein the access devices comprise ovonic threshold devices.

13. The memory array of claim 10 wherein the areas of the individual memory cell units along the planes are 2F 2 relative to wordlines, bitlines, access devices and spaces consumed by the memory cell units.

14. The memory array of claim 10 wherein the memory cell units comprise phase change material, and are directly between wordlines and bitlines; and wherein the only material directly between the wordlines and bitlines is the phase change material.

Assignees

• Micron Technology Inc

Inventors

• Liu Zengtao T

Classifications

• G01R33/1284

  Spin resolved measurements; Influencing spins during measurements, e.g. in spintronics devices · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G01R33/24

  for measuring direction or magnitude of magnetic fields or magnetic flux · CPC title