Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US9412306B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9412306-B2 |
| Application number | US-201414203043-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 10, 2014 |
| Priority date | Jul 9, 2013 |
| Publication date | Aug 9, 2016 |
| Grant date | Aug 9, 2016 |
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A driving apparatus includes: a plurality of shift registers disposed at a plurality of stages, respectively, where each of the shift registers includes: a first driver which generates an intermediate output signal and a first output signal based on a first signal, where the first driver includes: an input signal terminal, to which the first signal is applied; and an inversion input signal terminal, to which a second signal, which is an inverted signal of the first signal, is applied; and a second driver which receives the first output signal and generates a second driver output signal having a pulse voltage at a first level based on the first output signal and a pulse voltage at a second level based on a first clock signal or a second clock signal.
Opening claim text (preview).
What is claimed is: 1. A driving apparatus comprising: a plurality of shift registers disposed at a plurality of stages, respectively, wherein each of the shift registers comprises: a first driver which generates an intermediate output signal and a first output signal based on a first signal, wherein the first driver comprises: an input signal terminal, to which the first signal is applied; and an inversion input signal terminal, to which a second signal, which is an inverted signal of the first signal, is applied; and a second driver which receives the first output signal and generates a second driver output signal having a pulse voltage at a first level based on the first output signal and a pulse voltage at a second level based on a first clock signal or a second clock signal, wherein the first signal comprises a first input signal, a second input signal, a first inversion input signal, which is an inverted signal of the first input signal, and a second inversion input signal, which is an inverted signal of the second input signal. 2. The driving apparatus of claim 1 , wherein a pulse signal of the intermediate output signal and a pulse signal of the first output signal are inverted to each other, and the pulse voltage of the first output signal is substantially equal to a pulse voltage of the first signal. 3. The driving apparatus of claim 1 , wherein the first input signal, the second input signal, the first inversion input signal and the second inversion input signal are input to input signal terminals of four consecutive stages of the shift registers, respectively. 4. The driving apparatus of claim 3 , wherein inversion input signal terminals of the four consecutive stages of the shift registers receive the first inversion input signal, the second inversion input signal, the first input signal and the second input signal, respectively. 5. The driving apparatus of claim 1 , wherein the intermediate output signal of a shift register at a stage of the stages is transferred to the first driver of a shift register at a second next stage of the stages in a forward drive of the shift registers. 6. The driving apparatus of claim 1 , wherein the intermediate output signal of a shift register at a stage of the stages is transferred to the first driver of a shift register at a second previous stage of the stages in a backward drive of the shift registers. 7. The driving apparatus of claim 1 , wherein the first level is a predetermined high level, and the second level is a predetermined low level. 8. The driving apparatus of claim 1 , wherein the second driver output signal comprises: a second output signal having the pulse voltage at the second level based on one of the first clock signal and the second clock signal; and a third output signal having the pulse voltage at the second level based on the other of the first clock signal and the second clock signal. 9. The driving apparatus of claim 8 , wherein the second output signal of a shift register at a stage of the stages is transferred to the second driver of a shift register at a next stage of the stages in a forward drive of the shift registers. 10. The driving apparatus of claim 8 , wherein the second output signal of a shift register at a stage of the stages is transferred to the second driver of a shift register at a previous stage of the stages in a forward drive of the shift registers. 11. The driving apparatus of claim 1 , wherein a first control signal which controls a forward drive of the shift registers, is input to the first driver, and a second control signal which controls a backward drive of the shift registers and is an inverted signal of the first control signal, is input to the second driver. 12. The driving apparatus of claim 1 , wherein the first output signal controls the pulse voltage at the first level of the second driver output signal, and has a voltage level corresponding to a gate-on voltage level of a transistor in the second driver. 13. The driving apparatus of claim 1 , wherein the first driver further comprises: a first control signal terminal, to which a first control signal, which controls a forward drive of the shift registers, is applied; a second control signal terminal, to which a second control signal, which control a backward drive of the shift registers, is applied, a first forward driving signal terminal, to which a forward start signal of the first driver or the intermediate output signal of a second previous stage is applied, and a first backward driving signal terminal, to which a backward start signal of the first driver or the intermediate output signal of a second next stage is applied; and the second driver comprises: a first clock signal clock terminal, to which one of the first clock signal and the second clock signal is applied; a second clock signal terminal, to which the other of the first clock signal and the second clock signal is applied; the first control signal terminal; the second control signal terminal; a second forward driving signal terminal, to which the forward start signal of the second driver or the second driver output signal of the second driver at a first previous stage is applied; and a second backward driving signal to which a backward start signal of the second driver or the second driver output signal of the second driver at a first next stage is applied. 14. The driving apparatus of claim 13 , wherein the first driver further comprises a retain signal terminal, to which a retain signal, which controls a transfer of a predetermined bias voltage to a gate electrode of a transistor of the first driver, is applied. 15. The driving apparatus of claim 14 , wherein the predetermined bias voltage comprises a power source voltage with a high potential or a low potential. 16. The driving apparatus of claim 13 , wherein the first driver further comprises: a first switch which transfers a pulse voltage of the forward start signal of the first driver or the intermediate output signal at the second previous stage based on the first control signal; a second switch which transfers a pulse voltage of the backward start signal of the first driver or the intermediate output signal at the second next stage based on the first control signal; a third switch connected to a first common node, to which the first switch and the second switch are connected, and which transfers a signal applied to the first common node to a first node based on the first signal; a fourth switch which transfers a first power source voltage at a predetermined high potential to a second node based on the first signal; a fifth switch which transfers the pulse voltage of the second signal to the second node based on the voltage transferred to the first common node; a sixth switch which transfers the first power source voltage to a third node based on the voltage transferred to the second node; a seventh switch which transfers a second power source voltage at a predetermined low potential to the third node based on the first signal; an eighth switch which transfers the first power source voltage to a fourth node based on the voltage transferred to the third node; a ninth switch which transfers the second power source voltage to the fourth node based on the voltage transferred to the second node; a tenth switch which transfer the first power source voltage to a fifth node based on the voltage transferred to the fourth node; an eleventh switch which transfers the second power source voltage to the fifth node based on the voltage transferred to th
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with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title
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