Asynchronous FIFO buffer for memory access

Patent metadata

Field	Value
Publication number	US-9411722-B2
Application number	US-201414193917-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Mar 4, 2013
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received.

First claim

What is claimed is:

1. A non-volatile storage device, comprising:
a memory array;
a data interface;
a read enable interface configured to receive a read enable signal, wherein the read enable signal defines how data to be read from the memory array should be clocked out of the non-volatile storage device on the data interface;
an asynchronous first-in first-out (FIFO) buffer coupled to the data interface, the read enable interface, and the memory array, wherein the asynchronous FIFO buffer comprises a read clock input and a write clock input, wherein the read clock input is configured to receive the read enable signal, wherein the write clock input is configured to receive a write clock, wherein the write clock is a delayed version of the read enable signal that is asynchronous to the read enable signal provided to the read clock input, wherein the asynchronous FIFO buffer is configured to input data from the memory array in accordance with the write clock, wherein the asynchronous FIFO buffer is configured to output data in accordance with the read enable signal; and
control logic configured to provide the data output from the asynchronous FIFO buffer onto the data interface.

2. The non-volatile storage device of claim 1 , wherein the control logic is configured to suspend output of data from the asynchronous FIFO buffer in response to detecting an emptiness condition of the asynchronous FIFO buffer.

3. The non-volatile storage device of claim 1 , wherein the control logic is configured to:
detect an emptiness condition of the asynchronous FIFO buffer; and
prevent data from the memory array from being input to the asynchronous FIFO buffer if the emptiness condition is not met.

4. The non-volatile storage device of claim 1 , wherein the non-volatile storage device comprises a memory die and a memory controller;
wherein the memory array and the asynchronous FIFO buffer are on the memory die, wherein the data interface and the read enable interface are part of interface between the memory die and the memory controller.

5. The non-volatile storage device of claim 1 , wherein the memory array is a 3D memory array.

6. The non-volatile storage device of claim 4 , wherein the memory die further comprises a page register coupled to the memory array, wherein the control logic is configured to:
receive a read command and an address for data to be read from the memory array;
read the memory array at the address and temporarily store the data that is accessed from the memory array in the page register; and
pre-fetch portions of the data from the page register into the asynchronous FIFO buffer prior to a read enable signal first being received on the read enable interface following the read command.

7. The non-volatile storage device of claim 6 , wherein the asynchronous FIFO comprises a read pointer and a write pointer, wherein the read pointer points to a location of data in the asynchronous FIFO buffer to be output in accordance with the read enable signal, wherein the write pointer points to a location of data in the asynchronous FIFO buffer to write from the page register in accordance with the write clock.

8. The non-volatile storage device of claim 1 , wherein the control logic is further configured to pre-fetch data from the memory array into the asynchronous FIFO buffer prior to the read enable signal first being received on the read enable interface following a read command to read the data from the memory array.

9. The non-volatile storage device of claim 8 , wherein the control logic is further configured to:
transfer data from the memory array to a memory array buffer in response to receiving the read command and an address of data to be read from the memory array; and
pre-fetch portions of the data from the memory array buffer into the asynchronous FIFO buffer prior to a first transition of the read enable signal on the read enable interface following the read command.

10. A method of operating non-volatile storage device, comprising:
receiving a command to read data from a memory array of the non-volatile storage device;
receiving an address of the data to be read from the memory array;
receiving a read enable signal on a read enable interface of the non-volatile storage device, wherein the read enable signal defines how the data to be read should be clocked on to a data interface of the non-volatile storage device;
providing the read enable signal to an asynchronous first-in-first-out (FIFO) buffer;
outputting data from the asynchronous FIFO buffer in accordance with the read enable signal provided to the asynchronous FIFO buffer;
receiving a write clock signal at the asynchronous FIFO buffer, wherein the write clock signal is a delayed version of the read enable signal and is asynchronous from the read enable signal that is received at the asynchronous FIFO buffer;
inputting data from the memory array to the asynchronous FIFO buffer in accordance with the write clock signal; and
providing the data that is output from the asynchronous FIFO buffer to the data interface of the non-volatile storage device.

11. The method of claim 10 , wherein the inputting data from the memory array to the asynchronous FIFO buffer in accordance with the write clock signal comprises:
detecting an emptiness condition of the asynchronous FIFO buffer; and
preventing data from being input to the asynchronous FIFO buffer if the emptiness condition is not met.

12. The method of claim 10 , wherein the outputting data from the asynchronous FIFO buffer in accordance with the read enable signal provided to the asynchronous FIFO buffer comprises:
detecting an emptiness condition of the asynchronous FIFO buffer; and
suspending the outputting of data from the asynchronous FIFO buffer in response to detecting the emptiness condition.

13. The method of claim 10 , further comprising:
pre-fetching data from the memory array into an asynchronous first-in first-out (FIFO) buffer in accordance with the address, wherein the pre-fetching data occurs prior to first receiving the read enable signal following the read command.

14. The method of claim 13 , wherein the pre-fetching data from the memory array into the asynchronous FIFO buffer comprises:
transferring data from the memory array to a memory array buffer in response to receiving an address of data to be read from the memory array; and
pre-fetching portions of the data from the memory array buffer into the asynchronous FIFO buffer prior to the read enable signal first being received on the read enable interface.

15. A non-volatile storage device, comprising:
a 3D memory array having variable resistive memory cells;
a data interface;
a read enable interface that receives a read enable signal, wherein the read enable signal defines how data to be read from the memory array should be clocked out of the non-volatile storage device on the data interface;
an asynchronous first-in first-out (FIFO) buffer coupled to the data interface, the read enable interface, and the memory array, the asynchronous FIFO buffer having a read clock input and a write clock input, wherein the read clock input receives the read enable signal, wherein the write clock input receives a write clock that is asynchronous from the read enable signal, wherein the write clock is a delayed version of the read enable signal, wherein the asynchronous FIFO buffer inputs data from the memory array in accordance with the write clock, wherein the asynchronous FIFO buffer outputs data in accordance with the read enable signal; and
control logic that provides the data output from the asynchronous FIFO b

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Yap Kian-Chin Alex

Classifications

• G11C2207/2281

  Timing of a read operation · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C7/1066

  Output synchronization · CPC title