Providing hardware resources having different reliabilities for use by an application

Patent metadata

Field	Value
Publication number	US-9411674-B2
Application number	US-72730510-A
Country	US
Kind code	B2
Filing date	Mar 19, 2010
Priority date	Mar 19, 2010
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

Power management functionality is described for implementing an application in an energy-efficient manner, without substantially degrading overall performance of the application. The functionality operates by identifying at least first data and second data associated with the application. The first data is considered to have a greater potential impact on performance of the application compared to the second data. The functionality then instructs a first set of hardware-level resources to handle the first data and a second set of hardware-level resources to handle the second data. The first set of hardware-level resources has a higher reliability compared to the second set of hardware-level resources. In one case, the first and second hardware-level resources comprise DRAM memory units. Here, the first set of hardware-level resources achieves greater reliability than the second set of hardware-level resources by being refreshed at a higher rate than the second set of hardware-level resources.

First claim

What is claimed is:

1. A method, implemented by computing functionality, for executing an application, the method comprising:
identifying at least first data and second data associated with the application, corruption of the first data having a first impact on a performance of the application, and corruption of the second data having a second impact on the performance of the application, the first impact being assessed as less preferable than the second impact based on at least one assessment factor;
allocating virtual pages of memory to the first data and the second data;
using an operating system page table to map the virtual pages of memory to physical pages of memory storing the first data and the second data,
wherein the operating system page table maps a first virtual page of memory to a first physical page of memory storing the first data and a second virtual page of memory to a second physical page of memory storing the second data; and
instructing at least one memory unit to refresh the first physical page of memory storing the first data at a first rate and to refresh the second physical page or memory storing the second data at a second rate.

2. The method of claim 1 , wherein said instructing achieves at least one performance objective relating to conservation of energy.

3. The method of claim 1 , wherein the at least one memory unit includes a first memory unit storing the first physical page and a second memory unit storing the second physical page.

4. The method of claim 1 , wherein the at least one memory unit comprises a DRAM memory device having a first partition storing the first physical page and a second partition storing the second physical page.

5. The method of claim 1 , wherein said identifying comprises receiving designations provided in application code associated with the application, the designations identifying at least one of the first data and the second data.

6. The method of claim 1 , wherein said at least one assessment factor is based on an assessment made by a user.

7. The method of claim 1 , wherein the first physical page refreshes at a cycle time of approximately 32 milliseconds.

8. The method of claim 1 , where the second physical page refreshes at a cycle time of approximately one second.

9. The method of claim 1 , wherein both the first rate and the second rate are non-zero.

10. The method of claim 1 , wherein the computing functionality is provided by a mobile device, and wherein said instructing is invoked when the mobile device enters a low power mode of operation.

11. The method of claim 1 , wherein the computing functionality is provided by a server in a data center.

12. Functionality for achieving a performance objective, the functionality comprising:
software-level resources; and
hardware-level resources,
wherein the software-level resources, in conjunction with the hardware-level resources, implement an application;
the hardware-level resources comprising:
a first set of memory resources dynamically designated to refresh at a first non-zero rate for handling first data associated with the application; and
a second set of memory resources dynamically designated to refresh at a second non-zero rate for handling second data associated with the application,

corruption of the first data having a greater impact on a performance of the application than corruption of the second data, and
the first set of memory resources refreshing at the first non-zero rate having a higher reliability compared to the second set of memory resources refreshing at the second non-zero rate,
the software-level resources comprising an operating system configured to use a page table to map a first virtual page of memory storing the first data to a first physical page of memory on the first set of memory resources and to map a second virtual page of memory storing the second data to a second physical page of memory on the second set of memory resources.

13. The functionality of claim 12 , embodied as a mobile device.

14. The functionality of claim 12 , embodied as a server in a data center.

15. The functionality of claim 12 , wherein the first set of memory resources comprises a first dynamic random-access memory device and the second set of memory resources comprises a second dynamic random-access memory device.

16. A mobile device comprising:
memory configured to provide different refresh rates for physical pages of memory;
a processing device; and
instructions which, when executed by the processing device, cause the processing device to:
allocate a first virtual page of memory to first data and a second virtual page of memory to second data, the first data and the second data having different associated impacts when corrupted;
use an operating system page table to map the first virtual page of memory to a first physical page of memory and to map the second virtual page of memory to a second physical page of memory;
cause the first physical page of memory to store the first data;
cause the second physical page of memory to store the second data;
instruct the memory to periodically refresh the first physical page of memory storing the first data at a first refresh rate; and
instruct the memory to periodically refresh the second physical page of memory at a second refresh rate that is lower than the first refresh rate.

17. The mobile device of claim 16 , wherein the instructions, when executed by the processing device, cause the processing device to:
allocate heap memory for data storage on the memory;
partition the heap memory into a first heap portion having the first data and a second heap portion having the second data; and
designate the first heap portion to be refreshed at the first refresh rate and the second heap portion to be refreshed at the second refresh rate.

18. The mobile device of claim 17 , wherein the instructions, when executed by the processing device, cause the processing device to:
allocate the first heap portion responsive to a first call to a first dynamic memory allocation function; and
allocate the second heap portion responsive to a second call to a second dynamic memory allocation function that is different than the first dynamic memory allocation function.

19. The mobile device of claim 16 , wherein the instructions, when executed by the processing device, cause the processing device to:
load the first data and the second data as global data upon initial loading of an application that defines the first data and the second data as global and annotates the first data and the second data to have different refresh rates.

Assignees

• Pattabiraman Karthik
• Moscibroda Thomas
• Zorn Benjamin G
• Liu Song
• Microsoft Technology Licensing Llc

Inventors

• Pattabiraman Karthik
• Moscibroda Thomas
• Zorn Benjamin G
• Liu Song

Classifications

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F2212/1028

  Power efficiency · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title