Load balance connections per server in multi-core/multi-blade system

Patent metadata

Field	Value
Publication number	US-9411656-B2
Application number	US-48936609-A
Country	US
Kind code	B2
Filing date	Jun 22, 2009
Priority date	Jun 22, 2009
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.

First claim

We claim:

1. A method comprising:
aggregating local counter values associated with a first set of processors, thereby creating a first set of aggregated local counter values;
aggregating local counter values associated with a second set of processors, thereby creating a second set of aggregated local counter values; and then
aggregating the first and second sets of aggregated local counter values, thereby creating a global set of aggregated counter values; and
performing a load balancing with the first and second sets of processors in response to the global set of aggregated counter values.

2. The method of claim 1 , further comprising displaying the global set of aggregated counter values with a management processor, wherein the management processor does not perform any of the aggregating steps.

3. The method of claim 1 , wherein the first set of processors are located on a first blade and the second set of processors are located on a second blade, the method further comprising:
aggregating the local counter values associated with the first set of processors on the first blade; and
aggregating the local counter values associated with the second set of processors on the second blade.

4. The method of claim 3 , further comprising
transferring the second set of aggregated local counter values from the second blade to the first blade; and
aggregating the first and second sets of aggregated local counter values on the first blade.

5. The method of claim 4 , further comprising:
transferring the global set of aggregated counter values from the first blade to the second blade; and then
distributing the global set of aggregated counter values to the second set of processors.

6. The method of claim 4 , further comprising distributing the global set of aggregated counter values to the first set of processors on the first blade.

7. The method of claim 4 , further comprising:
transferring the global set of aggregated counter values to a management card separate from the first and second blades; and then
using the management card to display the global set of aggregated counter values.

8. A blade for a network device comprising:
a plurality of processors;
a plurality of local counter memories, each storing local counter values associated with a corresponding one of the processors;
an accumulator circuit that receives and aggregates the local counter values from each of the local counter memories; and
a control line coupling the accumulator circuit to an external connector of the blade, wherein the control line carries a control signal that synchronizes the aggregation of the local counter values within the network device.

9. The blade of claim 8 , further comprising a plurality of global counter memories, each associated with a corresponding one of the processors, and each storing a set of aggregated local counter values.

10. The blade of claim 8 , further comprising a local accumulator memory coupled to the accumulator circuit, wherein the local accumulator memory stores aggregated local counter values provided by the accumulator circuit.

11. The blade of claim 10 , further comprising means for routing the aggregated local counter values off of the blade.

12. The blade of claim 8 , further comprising a switching circuit coupling the processors to the accumulator circuit and to one or more links coupled to external connectors of the blade.

13. A network device comprising:
a plurality of blades, each blade including:
a plurality of processors that route requests received by the network device, wherein each of the processors maintains a set of local counter values; and
an accumulator circuit that periodically receives and aggregates the sets of local counter values maintained by the processors of the blade.

14. The network device of claim 13 , further comprising a control line coupling the accumulator circuits of the plurality of blades, wherein the control line carries a control signal that synchronizes the accumulator circuits.

15. The network device of claim 13 , wherein each of the blades further comprises a local accumulator memory that stores aggregated sets of local counter values created by the accumulator circuit of the blade.

16. The network device of claim 15 , further comprising means for transferring the aggregated sets of local counter values to a single one of the blades.

17. A method comprising:
aggregating a first set of local counter values associated with a first set of processors at a first frequency, thereby creating a first set of aggregated local counter values;
aggregating a second set of local counter values associated with the first set of processors at a second frequency, thereby creating a second set of aggregated local counter values, wherein the first frequency is greater than the second frequency;
aggregating a third set of local counter values associated with a second set of processors at the first frequency, thereby creating a third set of aggregated local counter values;
aggregating a fourth set of local counter values associated with the second set of processors at the second frequency, thereby creating a fourth set of aggregated local counter values;
aggregating the first and third sets of aggregated local counter values, thereby creating a first global set of aggregated counter values; and
performing a load balancing with the first and second sets of processors in response to the first global set of aggregated counter values.

18. The method of claim 17 , further comprising, aggregating the second and fourth sets of aggregated local counter values, thereby creating a second global set of aggregated counter values.

Assignees

• Jindal Avinash
• Bansal Deepak
• Moy Sam Htin
• Cheung David
• Wang Bing
• Kancherla Mani
• Devarapalli Sridhar
• Brocade Comm Systems Inc

Inventors

• Jindal Avinash
• Bansal Deepak
• Moy Sam Htin
• Cheung David
• Wang Bing
• Kancherla Mani
• Devarapalli Sridhar

Classifications

• G06F9/5083 Primary

  Techniques for rebalancing the load in a distributed system · CPC title