System and method for barrier command monitoring in computing systems

US9411633B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9411633-B2
Application numberUS-201313952331-A
CountryUS
Kind codeB2
Filing dateJul 26, 2013
Priority dateJul 27, 2012
Publication dateAug 9, 2016
Grant dateAug 9, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A computing system for handling barrier commands includes a memory, an interface, and a processor. The memory is configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command. The interface is coupled to the memory and is configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier spreading range and receive a barrier completion notification messages from the target computing system. The pre-barrier computing probe is configured to instruct the target computing system to monitor a status of a transaction that needs to be executed for the barrier command to be completed. The processor is coupled to the interface and is configured to determine a status of the barrier command based on the received barrier completion notification messages.

First claim

Opening claim text (preview).

What is claimed is: 1. A computing system comprising: a memory configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command, wherein the memory is configured to store a post-barrier spreading range that includes an indication of at least one of the target computing system and other target computing systems that receive early-forwarded transactions, wherein the early-forwarded transactions comprise transactions that can only be executed after the barrier command is completed; an interface coupled to the memory and configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier spreading range and receive a barrier completion notification message from the target computing system, wherein the pre-barrier computing probe is configured to instruct the target computing system to monitor a status of a transaction that needs to be executed for the barrier command to be completed, wherein the face is configured to send a post-barrier start notice to at least one of the target computing system and the other target computing systems that receive the early-forwarded transactions when the barrier command is completed; and a processor coupled to the interface and configured to determine a status of the barrier command based on the received barrier completion notification message, wherein the processor is configured to determine that the barrier command is completed when all target computing systems that are sent transactions that need to be executed for the barrier command to be completed have indicated at least one of finished transaction execution and guarantee of finished transaction execution behavior. 2. The computing system of claim 1 , wherein the barrier completion notification message is received from the target computing system, and wherein the barrier completion notification message indicates that the target computing system has executed the transaction that needs to be executed for the barrier command to be completed or that the barrier completion notification message indicates that the target computing system is guaranteed to behave like it has executed the transaction that needs to be executed for the barrier command to be completed. 3. The computing system of claim 1 , wherein the interface is configured to send transactions that can only be executed after the barrier command is completed to the target computing system when the processor determines that the barrier command is completed. 4. The computing system of claim 1 , wherein the processor is configured to identify transactions being forwarded to the target computing system before a completion of a required barrier command, wherein the interface is configured to send the identified transactions to the target computing system with an indication that the transactions are early-forwarded transactions, wherein the indication that the transactions are early-forwarded transactions comprises the transactions including early-forwarded attributes, or wherein the indication that the transactions are early-forwarded transactions comprises the transactions being locked such that the transactions cannot be executed until being unlocked with a key. 5. The computing system of claim 1 , wherein the pre-barrier spreading range identifies the target computing system and any other target computing systems that receive transactions that need to be executed before the barrier command is completed, and wherein the target computing system and the other target computing systems are either pre-determined or are dynamically determined by the processor. 6. The computing system of claim 1 , wherein the barrier command is associated with a program that comprises multiple barrier commands and multiple target computing systems, and wherein the pre-barrier spreading range comprises addresses or other identifiers of at least one of the target computing system and the other target computing systems associated with the barrier command and identifiers of transactions that are associated with the multiple barrier commands. 7. A computing system comprising: an interface configured to receive a pre-barrier computing probe from a source computing system and send a barrier completion notification message to the source computing system, wherein the pre-barrier computing probe instructs the computing system to monitor a status of a transaction that is associated with a barrier command, and wherein the barrier completion notification message indicates that the transaction associated with the barrier command has been executed by the computing system or that the computing system guarantees that it will behave like it has executed the transaction; and a processor coupled to the interface and configured to wait to execute an early-forwarded transaction until a post-barrier start notice is received from the source computing system, wherein the early-forwarded transaction comprises a transaction that can only be executed after the barrier command is completed, and wherein the post-barrier start notice indicates that the barrier command associated with the early-forwarded transaction has been completed. 8. The computing system of claim 7 , wherein the processor is configured to execute the transaction after the interface has received a key to unlock the transaction from the source computing system. 9. The computing system of claim 7 , wherein the pre-barrier computing probe identifies a number of transactions that need to be executed for the barrier command to be completed, and wherein the computing system is configured to send the source computing system the barrier completion notification message when all the transactions have been executed or when the computing system can guarantee that it will behave like it has executed all of the transactions. 10. The computing system of claim 7 , wherein the computing system is configured to receive a plurality of pre-barrier computing probes, wherein each of the pre-barrier computing probes is associated with a different barrier command, and wherein each pre-barrier computing probe identifies a particular barrier command associated with the pre-barrier computing probe. 11. A method comprising: identifying a transaction associated with a completion of a barrier command; identifying a target computing system associated with the transaction; sending the target computing system a pre-barrier computing probe, wherein the pre-barrier computing probe instructs the target computing system to monitor an execution status of the transaction associated with the completion of the barrier command; receiving a barrier completion notification message from the target computing system, wherein the barrier completion notification message indicates that the target computing system has executed the transaction associated with the completion of the barrier command or that the target computing system can guarantee that it will behave like it has executed the transaction associated with the completion of the barrier command; determining whether the barrier command is completed based on the received barrier completion notification message, wherein the barrier command is determined to have been completed when all target computing systems that were sent pre-barrier computing probes have returned their barrier completion notification messages; and sending a post-barrier start notice to at least one of the target computing system and other target computing systems that receive early-forwarded transactions when the barrier command is completed, wherein the early-forwarded transactions comprise transactions at can only be executed after the barrier command is completed.

Assignees

Inventors

Classifications

  • G06F9/466Primary

    Transaction processing · CPC title

  • G06F9/522Primary

    Barrier synchronisation · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9411633B2 cover?
A computing system for handling barrier commands includes a memory, an interface, and a processor. The memory is configured to store a pre-barrier spreading range that identifies a target computing system associated with a barrier command. The interface is coupled to the memory and is configured to send a pre-barrier computing probe to the target computing system identified in the pre-barrier s…
Who is the assignee on this patent?
Futurewei Technologies Inc
What technology area does this patent fall under?
Primary CPC classification G06F9/466. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).